Digital still camera system and method

• US 20030222998A1
• Filed: 05/28/2002
• Published: 12/04/2003
• Est. Priority Date: 12/20/2000
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Osamoto, Akira, Inamori, Shinri, Yamauchi, Satoru, Koshiba, Osamu
• Application Number:
  US10/156,422
• Publication Number:
  US 20030222998A1
• Time in Patent Office: Days
• US Class Current: 348/262
• CPC Class Codes: G06T 3/4015 Image demosaicing, e.g. colour filter arrays [CFA] or Bayer patterns
• CPC Class Codes: G06T 5/20 using local operators
• CPC Class Codes: H04N 1/4074 using histograms
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 2101/00 Still video cameras
• CPC Class Codes: H04N 23/635 Region indicators; Field of view indicators
• CPC Class Codes: H04N 23/67 Focus control based on electronic image sensor signals
• CPC Class Codes: H04N 23/843 Demosaicing, e.g. interpolating colour pixel values
• CPC Class Codes: H04N 25/134 based on three different wavelength filter elements
• CPC Class Codes: H04N 25/136 using complementary colours
• CPC Class Codes: H04N 5/772 the recording apparatus and the television camera being placed in the same enclosure
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence
• CPC Class Codes: H04N 9/8042 involving data reduction

Abstract

Digital Camera includes separate preview engine, burst mode compression/decompression engine, image pipeline, CCD plus CCD controller, and memory plus memory controller. ARM microprocessor and DSP share control, and preview engine register provide parameters for preview engine image processing hardware.

Claims

1. An integrated circuit for a digital camera, comprising:

(a) a first programmable processor programmed to run control functions, said first processor coupled to a user interface, a controller for memory, and a controller for image acquisition;

(b) a second programmable processor programmed to run image processing functions, said second processor coupled to said first processor; and

(c) a preview engine coupled to said first processor, to said controller for image acquisition, and to said controller for memory;

(d) wherein said preview engine has a first mode with input coupled to said controller for image acquisition and with RGB image processing functions plus a second mode with input coupled to said controller for memory and with a YCbCr resizing function.

2. An integrated circuit for a digital camera, comprising:

(a) a first programmable processor programmed to run control functions, said first processor coupled to a user interface, a controller for memory, and a controller for image acquisition;

(b) a second programmable processor programmed to run image processing functions, said second processor coupled to said first processor; and

(c) a preview engine coupled to said first processor, to said controller for image acquisition, and to said controller for memory;

(d) wherein said preview engine includes registers and image processing hardware with the contents of said registers providing parameters for said image processing hardware.