Thin film transistor array panel for liquid crystal display having pixel electrode

• US 20030223019A1
• Filed: 12/12/2002
• Published: 12/04/2003
• Est. Priority Date: 06/03/2002
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kong, Hyang-Shik, Kim, Dong-Gyu, Kim, Jang-Soo
• Granted Patent: US 7,145,620 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/133784 by rubbing
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 2201/123 pixel

Abstract

A TFT array panel includes an insulating substrate, a gate line and a storage electrode line formed thereon. The gate line and the storage electrode line are covered with a gate insulating layer, and a semiconductor island is formed on the gate insulating layer. A pair of ohmic contacts are formed on the semiconductor island, and a data line and a drain electrode are formed thereon. The data line and the drain electrode are covered with a passivation layer having a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer and connected to the drain electrode through the contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to the lower right corner of the TFT array panel or the pixel electrode. The pixel electrode has approximately a rectangular shape and overlaps the gate line and the data line. The pixel electrode has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or the data line.

Claims

1. A thin film transistor array panel for a liquid crystal display, comprising:

a substrate;

a plurality of signal lines including a gate line and a data line insulated from each other, the plurality of signal lines being provided on the substrate;

a switching element electrically connected to the gate line and the data line;

a pixel electrode electrically connected to the switching element and overlapping at least one of the signal lines to form at least one overlapping area; and

an alignment layer covering the pixel electrode,

wherein at least one portion of the at least one overlapping area is wider than other portions of the at least one overlapping area.

2. The thin film transistor array panel of claim 1, wherein the alignment layer is positioned for receiving a rubbing action in a predetermined direction, and the wider overlapping area is disposed proximal to a starting position of the rubbing action of the alignment layer.

3. The thin film transistor array panel of claim 1, wherein the pixel electrode has an expansion forming the at least one portion of the at least one overlapping area.

4. The thin film transistor array panel of claim 1, wherein the pixel electrode has a plurality of major edges, and at least one of the major edges proceeds into the at least one of the gate line and the data line more deeply than other major edges to form the at least one portion of the at least one overlapping area.

5. The thin film transistor array panel of claim 1, wherein the switching element comprises a semiconductor layer electrically connected to the gate line and the pixel electrode, and the semiconductor layer extends along the data line.

6. The thin film transistor array panel of claim 5, wherein the switching element further comprises an ohmic contact interposed between the semiconductor layer and the data line.

7. The thin film transistor array panel of claim 1, further comprising:

a storage electrode separated from the signal lines; and

a storage conductor electrically connected to the pixel electrode and overlapping the storage electrode via an insulating layer.

8. The thin film transistor array panel of claim 7, wherein the storage conductor is directly connected to the thin film transistor.

9. The thin film transistor array panel of claim 1, wherein the pixel electrode is located on the insulator and the thin film transistor is located under the insulator.

10. A thin film transistor array panel for a liquid crystal display, comprising:

a substrate;

a plurality of signal lines provided on the substrate and including a gate line and a data line;

a gate insulating layer interposed between the gate line and the data line;

a switching element electrically connected to the gate line and the data line;

a pixel electrode electrically connected to the switching element; and

a passivation layer interposed between the pixel electrode and the data line and between the pixel electrode and the gate line,

wherein the pixel electrode overlaps at least one of the signal lines to form at least one overlapping area and includes an expansion providing larger width of a portion of the at least one overlapping area than other portions of the at least one overlapping area.

11. The thin film transistor array panel of claim 10, wherein the at least one of the signal lines includes the gate line.

12. The thin film transistor array panel of claim 10, wherein the pixel electrode has substantially a rectangular shape with four major edges including first two major edges substantially parallel to the gate line and second two major edges substantially parallel to the data line, and a portion of the first two major edges form the expansion.

13. The thin film transistor array panel of claim 10, wherein the switching element comprises a semiconductor layer electrically connected to the gate line and the pixel electrode, and the semiconductor layer extends along the data line.

14. The thin film transistor array panel of claim 13, wherein the switching element further comprises an ohmic contact interposed between the semiconductor layer and the data line.

15. The thin film transistor array panel of claim 10, further comprising:

a storage electrode separated from the signal lines; and

a storage conductor electrically connected to the pixel electrode and located opposite the storage electrode with respect to the gate insulating layer to overlap the storage electrode.

16. The thin film transistor array panel of claim 15, wherein the storage conductor is directly connected to the thin film transistor.

17. The thin film transistor array panel of claim 10, wherein the pixel electrode is located on the passivation layer and the thin film transistor is located under the passivation layer.

18. A process for making a thin film array panel for a liquid crystal display, comprising:

forming a plurality of signal lines including a gate line and a data line on a substrate;

positioning a switching element to electronically connect to the gate line and the data line;

positioning a pixel electrode to overlap at least one of the signal lines to form at least one overlapping area;

positioning an alignment layer to cover the pixel electrode;

positioning an alignment layer having a starting point for receiving a rubbing process for orienting liquid crystals; and

forming an overlapping area wherein the pixel electrode overlaps at least one of the signal lines, said overlapping area having a wide portion which is wider than other portions.