Method and apparatus for active power factor correction with minimum input current distortion

• US 20030223255A1
• Filed: 05/31/2002
• Published: 12/04/2003
• Est. Priority Date: 05/31/2002
• Status: Active Grant

• Current Assignee: Green Power Technologies Ltd.
• Original Assignee: Green Power Technologies Ltd.
• Inventors: Ben-Yaakov, Shmuel, Zeltser, Ilya
• Granted Patent: US 6,728,121 B2
• Time in Patent Office: Days
• US Class Current: 363/89
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A method for reducing the harmonics contents of an input current drawn from a power line into an electrical system without sensing an input voltage, the method comprising providing an active power factor correction controller with a switch module having a main switch and a timing device, wherein the main switch has an on-time correlated with an on-duty cycle duration, and an off-time correlated with an off-duty cycle duration, and maintaining a linear relationship between the off-duty cycle duration and the input current by using the timing device; and an apparatus for active power factor correction with minimum input current distortion, comprising an active power factor correction assembly that includes a main switch and a timing device, wherein the main switch has associated therewith an on-time correlated with an on-duty cycle duration, and an off-time correlated with an off-duty cycle duration, and wherein the timing device generates the mentioned on-time and off-time, and linearization means for maintaining a linear relation between the off-duty cycle duration and the input current.

Claims

1. A method for reducing the harmonics contents of an input current drawn from a power line into an electrical system without sensing an input voltage, the method comprising:

a) providing an active power factor correction controller with a switch module having a main switch and a timing device, wherein said main switch has an on-time correlated with an on-duty cycle duration, and an off-time correlated with an off-duty cycle duration;

b) maintaining a linear relationship between said off-duty cycle duration and the input current by using said timing device.

2. The method of claim 1, wherein said maintaining step includes making said linear relationship dependent on the deviation of an output voltage from a pre-determined reference voltage.

3. The method of claim 1, wherein said timing device is selected from the group consisting from analog timing devices and digital timing devices.

4. The method of claim 1, wherein said timing device includes a ramp capacitor, and wherein said maintaining step further includes:

i. charging and discharging said ramp capacitor, said charging associated with a charge time and said discharging associated with a discharge time;

ii. providing linearization means; and

ii. using said linearization means to include said discharge time of said ramp capacitor in said on-time of said main switch.

5. The method of claim 2, further comprising the step of providing a non-linear feedback to said controller, wherein said non-linear feedback is provided by an output circuit referenced to said output voltage.

6. The method of claim 4, wherein said linearization is accomplished using a logic gate added to said controller.

7. The method of claim 4, wherein said step of charging and discharging said capacitor is done with a current controlled by an amplified difference between said output voltage and a reference voltage.

8. The method of claim 5, wherein said output circuit is comprised of resistors R₁, R₂, and R₃, diodes D₃ and D₄, and a capacitor C₂ electrically connected as shown in FIG. 7.

9. The method of claim 6, further comprising blocking the gate pulses of said main switch when said output voltage reaches a level too high.

10. The method of claim 9, wherein said blocking is effected by adding a logic gate to said switch module.

11. The method of claim 9, further comprising the step of eliminating pulses of said discharge time if said on-duty cycle duration is smaller than a predetermined time.

12. The method of claim 1, further comprising adding at least one lossless snubber to said controller, said added at least one lossless snubber increasing the efficiency of said controller in reducing the harmonics content of the input current.

13. The method of claim 2, further comprising the step of adding an offset to the input current to obtain a combined signal, and making said off-time proportional to said combined signal.

14. An apparatus for active power factor correction with minimum input current distortion, comprising:

a) an active power factor correction assembly that includes a main switch and a timing device, wherein said main switch has associated therewith an on-time correlated with an on-duty cycle duration, and an off-time correlated with an off-duty cycle duration, and wherein said timing device generates said on-time and off-time; and

b) linearization means for maintaining a linear relationship between said off-duty cycle duration and the input current.

15. The apparatus of claim 14, further comprising control means for making said linear relationship dependent on the deviation of an output voltage from a pre-determined reference voltage.

16. The apparatus of claim 14, wherein said timing device is selected from the group consisting of digital timing devices and analog timing devices.

17. The apparatus of claim 16, wherein said analog timing devices include a ramp capacitor, and wherein said linearization means include a logic gate.

18. The apparatus of claim 15, further comprising a non-linear feedback network connected between said timing device and said output voltage to control the level of said output voltage, said non-linear network providing further reduction in the input current distortion.

19. The apparatus of claim 18, wherein said non-linear feedback network includes an output circuit comprised of resistors R1, R2, and R3, diodes D3 and D4, and a capacitor C2, electrically connected as shown in FIG. 7.

20. The apparatus of claim 14, wherein said assembly is implemented in modular construction.

21. The apparatus of claim 14, wherein a circuitry subsection of the apparatus is implemented in a monolithic microelectronic unit.

22. The apparatus of claim 14, wherein a circuitry subsection of the apparatus is implemented in a hybrid microelectronic unit.