Bit synchronizing circuit
First Claim
1. A bit synchronizing circuit that synchronizes serial data by a clock signal when transmitting bit data, comprising:
- a phase comparison clock generation unit for generating a plurality of clock signals based on a predetermined reference clock signal, each of the clock signals having a unique phase different from other clock signals, a plurality of edge detection units, each unit being for generating an edge signal that indicates an edge position of the serial data, wherein each of the detection units is supplied with a group of the clock signals, the group of the clock signals consisting of every predetermined number of the clock signals generated by the phase comparison clock generation unit, a clock judging unit for generating a synchronous timing signal based on the edge signal generated by each of -the edge detection units, and a clock selection unit for selecting a clock signal for writing that is suitable for a clock signal for synchronizing the serial data, the selection being made from the clock signals, each of which is in a different phase, based on the synchronous timing signal generated by the clock judging unit.
1 Assignment
0 Petitions
Accused Products
Abstract
A bit synchronizing circuit that provides highly reliable data transmission at a high speed is provided. The circuit facilitates testing by using a plurality of clock signals that are generated based on a reference clock signal, each of the clock signals having unique phases. The circuit selects one of the clock signals as a writing clock signal that is suitable for a clock signal for synchronizing serial data, based on a synchronous timing signal. The synchronous timing signal is generated based on an edge signal that is generated based on an edge position of serial data. The edge position is determined for a plurality of groups of the clock signals, each group consisting of clock signals chosen every predetermined number of the clock signals.
28 Citations
8 Claims
-
1. A bit synchronizing circuit that synchronizes serial data by a clock signal when transmitting bit data, comprising:
-
a phase comparison clock generation unit for generating a plurality of clock signals based on a predetermined reference clock signal, each of the clock signals having a unique phase different from other clock signals, a plurality of edge detection units, each unit being for generating an edge signal that indicates an edge position of the serial data, wherein each of the detection units is supplied with a group of the clock signals, the group of the clock signals consisting of every predetermined number of the clock signals generated by the phase comparison clock generation unit, a clock judging unit for generating a synchronous timing signal based on the edge signal generated by each of -the edge detection units, and a clock selection unit for selecting a clock signal for writing that is suitable for a clock signal for synchronizing the serial data, the selection being made from the clock signals, each of which is in a different phase, based on the synchronous timing signal generated by the clock judging unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
Specification