Method and apparatus for DC offset removal in a radio frequency communication channel

• US 20030224752A1
• Filed: 11/08/2002
• Published: 12/04/2003
• Est. Priority Date: 06/04/2002
• Status: Active Grant

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Rawlins, Gregory S., Sorrells, David F., Brown, Kevin, Rawlins, Michael W.
• Granted Patent: US 6,975,848 B2
• Time in Patent Office: Days
• US Class Current: 455/307
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A filter module for reducing a DC offset voltage in a radio frequency communication channel is described. A first capacitor is coupled between a first differential input node and a first differential output node. A second capacitor is coupled between a second differential input node and a second differential output node. An active variable resistor is coupled between the first differential output node and the second differential output node. The active variable resistor receives a control signal. The control signal adjusts the value of the active variable resistor, which adjusts the frequency response of the filter module. The rate at which the filter module reduces DC offset voltages is thereby adjusted. The filter module is also adaptable to single-ended applications.

Claims

1. A filter module for reducing a DC offset voltage, comprising:

a first capacitor coupled between a first differential input node and a first differential output node;

a second capacitor coupled between a second differential input node and a second differential output node; and

an active variable resistor coupled between said first differential output node and said second differential output node, wherein said active variable resistor receives a control signal.

2. The filter module of claim 1, wherein said active variable resistor comprises:

a first MOSFET transistor; and

a second MOSFET transistor coupled in parallel with said first MOSFET transistor.

3. The filter module of claim 1, wherein said active variable resistor comprises:

a first MOSFET transistor;

a second MOSFET transistor;

a third MOSFET transistor;

a fourth MOSFET transistor;

a first controlled current source; and

a second controlled current source;

wherein the first output node is coupled to a source of said first transistor, a source of said second transistor, and a gate of said third transistor;

wherein the second output node is coupled to a drain of said first transistor, a drain of said second transistor, and a gate of said fourth transistor;

wherein a drain of said third transistor and a drain of said fourth transistor are coupled to a reference voltage;

wherein a gate of said first transistor and a source of said third transistor are coupled to an output of said first controlled current source;

wherein a gate of said second transistor and a source of said fourth transistor are coupled to an output of said second controlled current source; and

wherein an input of said first controlled current source and an input of said second controlled current source are coupled to said control signal.

4. The filter module of claim 3, wherein said first controlled current source includes a fifth MOSFET transistor, wherein a gate of said fifth MOSFET transistor is coupled to said control signal, a source of said fifth MOSFET transistor is coupled to a second reference voltage, and a drain of said fifth MOSFET transistor is coupled to the gate of said first transistor and the source of said third transistor;

and

wherein said second controlled current source includes a sixth MOSFET transistor, wherein a gate of said sixth MOSFET transistor is coupled to said control signal, a source of said sixth MOSFET transistor is coupled to the second reference voltage, and a drain of said sixth MOSFET transistor is coupled to the gate of said second transistor and the source of said fourth transistor.

5. The filter module of claim 1, wherein said control signal is a periodic substantially ramp-shaped waveform.

6. The filter module of claim 5, wherein said substantially ramp-shaped waveform is an exponential waveform.

7. The filter module of claim 5, wherein at a first time during a cycle of said ramp-shaped waveform, said control signal causes said active variable resistor to have a first resistance value, and at a second time during said cycle of said ramp-shaped waveform, said control signal causes said active variable resistor to have a second resistance value, wherein said second time is after said first time.

8. The filter module of claim 7, wherein said second resistance value is greater than said first resistance value.

9. The filter module of claim 8, wherein a cutoff frequency of the filter module at the first time is a higher frequency than a cutoff frequency of the filter module at the second time.

10. The filter module of claim 9, wherein said first capacitor and said second capacitor acquire a DC offset voltage in a differential input signal more rapidly at the second time than at the first time.

11. The filter module of claim 7, wherein an amplitude of the ramp-shaped waveform is greater at the second time than at the first time.

12. The filter module of claim 5, wherein a first cycle of said ramp-shaped waveform has a substantially different maximum amplitude than a second cycle of said ramp-shaped waveform.

13. The filter module of claim 5, wherein a cycle of said ramp waveform has a duration of 10 μ

S.

14. The filter module of claim 5, wherein each cycle of said ramp waveform is initiated at an occurrence of a diversity transition.

15. The filter module of claim 1, further comprising a second resistor coupled between said first differential output node and said second differential output node.

16. The filter module of claim 1, further comprising a second resistor coupled in series with said active variable resistor between said first differential output node and said second differential output node.

17. The filter module of claim 1, wherein said filter module receives a baseband differential input signal.

18. The filter module of claim 17, wherein said baseband differential input signal is a modulated baseband differential input signal.

19. The filter module of claim 1, wherein the filter module reduces flicker noise in a differential input signal.

20. A filter module for reducing a DC offset voltage, comprising:

a capacitor coupled between an input signal and an output signal; and

an active variable resistor coupled between said output signal and a reference voltage, wherein said active variable resistor receives a control signal.

21. The filter module of claim 20, wherein said active variable resistor comprises:

a first MOSFET transistor; and

a second MOSFET transistor coupled in parallel with said first MOSFET transistor.

22. The filter module of claim 20, wherein said active variable resistor comprises:

a first MOSFET transistor;

a second MOSFET transistor;

a third MOSFET transistor;

a fourth MOSFET transistor;

a first controlled current source; and

a second controlled current source;

wherein the output signal is coupled to a source of said first transistor, a source of said second transistor, and a gate of said third transistor;

wherein the first reference voltage is coupled to a drain of said first transistor, a drain of said second transistor, and a gate of said fourth transistor;

wherein a drain of said third transistor and a drain of said fourth transistor are coupled to a second reference voltage;

wherein a gate of said first transistor and a source of said third transistor are coupled to an output of said first controlled current source;

wherein a gate of said second transistor and a source of said fourth transistor are coupled to an output of said second controlled current source; and

wherein an input of said first controlled current source and an input of said second controlled current source are coupled to said control signal.

23. The filter module of claim 22, wherein said first controlled current source includes a fifth MOSFET transistor, wherein a gate of said fifth MOSFET transistor is coupled to said control signal, a source of said fifth MOSFET transistor is coupled to a third reference voltage, and a drain of said fifth MOSFET transistor is coupled to the gate of said first transistor and the source of said third transistor;

and

wherein said second controlled current source includes a sixth MOSFET transistor, wherein a gate of said sixth MOSFET transistor is coupled to said control signal, a source of said sixth MOSFET transistor is coupled to the third reference voltage, and a drain of said sixth MOSFET transistor is coupled to the gate of said second transistor and the source of said fourth transistor.

24. The filter module of claim 20, wherein said control signal is a periodic substantially ramp-shaped waveform.

25. The filter module of claim 24, wherein said substantially ramp-shaped waveform is an exponential waveform.

26. The filter module of claim 24, wherein at a first time during a cycle of said ramp-shaped waveform, said control signal causes said active variable resistor to have a first resistance value, and at a second time during said cycle of said ramp-shaped waveform, said control signal causes said active variable resistor to have a second resistance value, wherein said second time is after said first time.

27. The filter module of claim 26, wherein said second resistance value is greater than said first resistance value.

28. The filter module of claim 27, wherein a cutoff frequency of the filter module at the first time is a higher frequency than a cutoff frequency of the filter module at the second time.

29. The filter module of claim 28, wherein said capacitor acquires a DC offset voltage in an input signal more rapidly at the second time than at the first time.

30. The filter module of claim 26, wherein an amplitude of the ramp-shaped waveform is greater at the second time than at the first time.

31. The filter module of claim 25, wherein a first cycle of said ramp-shaped waveform has a substantially different maximum amplitude than a second cycle of said ramp-shaped waveform.

32. The filter module of claim 25, wherein a cycle of said ramp waveform has a duration of 10 μ

S.

33. The filter module of claim 25, wherein each cycle of said ramp waveform is initiated at an occurrence of a diversity transition.

34. The filter module of claim 20, further comprising a second resistor coupled between said output signal and said first reference voltage.

35. The filter module of claim 20, further comprising a second resistor coupled in series with said active variable resistor between said output signal and said first reference voltage.

36. The filter module of claim 20, wherein said filter module receives a baseband input signal.

37. The filter module of claim 36, wherein said baseband input signal is a modulated baseband input signal.

38. The filter module of claim 37, wherein said filter module is located in an automatic gain control feedback loop.

39. The filter module of claim 20, wherein the filter module reduces flicker noise in the input signal.

40. An automatic gain control (AGC) feedback loop, comprising:

a rectifier that receives a first receiver channel signal and outputs a rectified signal;

a filter module that receives the rectified signal and outputs an AGC signal; and

an AGC amplifier that receives a second receiver channel signal and the AGC signal, and outputs a third receiver channel signal;

wherein said filter module includes

a capacitor coupled between said rectified signal and said AGC signal, and

an active variable resistor coupled between said AGC signal and a reference voltage, wherein said active variable resistor receives a control signal.

41. The AGC feedback loop of claim 40, wherein said rectifier is a full wave rectifier.

42. The AGC feedback loop of claim 40, wherein said rectifier is a half wave rectifier.

43. The AGC feedback loop of claim 40, wherein said active variable resistor comprises:

a first MOSFET transistor; and

a second MOSFET transistor coupled in parallel with said first MOSFET transistor.

44. The AGC feedback loop of claim 40, wherein said active variable resistor comprises:

a first MOSFET transistor;

a second MOSFET transistor;

a third MOSFET transistor;

a fourth MOSFET transistor;

a first controlled current source; and

a second controlled current source;

wherein the output signal is coupled to a source of said first transistor, a source of said second transistor, and a gate of said third transistor;

wherein the first reference voltage is coupled to a drain of said first transistor, a drain of said second transistor, and a gate of said fourth transistor;

wherein a drain of said third transistor and a drain of said fourth transistor are coupled to a second reference voltage;

wherein a gate of said first transistor and a source of said third transistor are coupled to an output of said first controlled current source;

wherein a gate of said second transistor and a source of said fourth transistor are coupled to an output of said second controlled current source; and

wherein an input of said first controlled current source and an input of said second controlled current source are coupled to said control signal.

45. The AGC feedback loop of claim 44, wherein said first controlled current source includes a fifth MOSFET transistor, wherein a gate of said fifth MOSFET transistor is coupled to said control signal, a source of said fifth MOSFET transistor is coupled to a third reference voltage, and a drain of said fifth MOSFET transistor is coupled to the gate of said first transistor and the source of said third transistor;

and

wherein said second controlled current source includes a sixth MOSFET transistor, wherein a gate of said sixth MOSFET transistor is coupled to said control signal, a source of said sixth MOSFET transistor is coupled to the third reference voltage, and a drain of said sixth MOSFET transistor is coupled to the gate of said second transistor and the source of said fourth transistor.

46. The AGC feedback loop of claim 40, wherein said control signal is a periodic substantially ramp-shaped waveform.

47. The filter module of claim 46, wherein said substantially ramp-shaped waveform is an exponential waveform.

48. The AGC feedback loop of claim 42, wherein at a first time during a cycle of said ramp-shaped waveform, said control signal causes said active variable resistor to have a first resistance value, and at a second time during said cycle of said ramp-shaped waveform, said control signal causes said active variable resistor to have a second resistance value, wherein said second time is after said first time.

49. The AGC feedback loop of claim 48, wherein said second resistance value is greater than said first resistance value.

50. The AGC feedback loop of claim 48, wherein a cutoff frequency of the filter module at the first time is a higher frequency than a cutoff frequency of the filter module at the second time.

51. The AGC feedback loop of claim 50, wherein said capacitor acquires a DC offset voltage in an input signal more rapidly at the second time than at the first time.

52. The AGC feedback loop of claim 48, wherein an amplitude of the ramp-shaped waveform is greater at the second time than at the first time.

53. The AGC feedback loop of claim 46, wherein a first cycle of said ramp-shaped waveform has a substantially different maximum amplitude than a second cycle of said ramp-shaped waveform.

54. The AGC feedback loop of claim 46, wherein a cycle of said ramp waveform has a duration of 10 μ

S.

55. The AGC feedback loop of claim 46, wherein each cycle of said ramp waveform is initiated at an occurrence of a diversity transition.

56. The AGC feedback loop of claim 40, further comprising a second resistor coupled between said output signal and said first reference voltage.

57. The AGC feedback loop of claim 40, further comprising a second resistor coupled in series with said active variable resistor between said output signal and said first reference voltage.

58. A method for reducing a DC offset voltage in a differential signal received across a first differential input node and a second differential input node, comprising the steps of:

(A) coupling a first capacitor between the first differential input node and a first differential output node;

(B) coupling a second capacitor between the second differential input node and a second differential output node; and

(C) varying the resistance of a variable resistor coupled between the first differential output node and the second differential output node according to a control signal.

59. The method of claim 58, wherein step (C) includes the step of:

(1) receiving a substantially ramp-shaped waveform cycle on the control signal.

60. The filter module of claim 59, wherein step (1) comprises the step of:

receiving an exponential waveform on the control signal.

61. The method of claim 60, wherein step (C) further comprises the steps of:

(2) causing the variable resistor to have a first resistance value at a first time during the ramp-shaped waveform cycle; and

(3) causing the variable resistor to have a second resistance value at a second time during the ramp-shaped waveform cycle.

62. The method of claim 61, wherein step (3) includes the step of:

causing the second resistance value to be greater than to the first resistance value.

63. The method of claim 61, wherein (3) includes the step of:

causing a cutoff frequency at the first time to be a higher frequency than a cutoff frequency at the second time.

64. The method of claim 63, further comprising the step of:

(D) acquiring a DC offset voltage in the first capacitor and the second capacitor more rapidly at the second time than at the first time.

65. The method of claim 60, wherein step (C) further includes the step of:

(2) receiving a second substantially ramp-shaped waveform cycle on the control signal.

66. The method of claim 65, wherein step (2) includes the step of:

causing an amplitude of the second substantially ramp-shaped waveform to be different from an amplitude of the first substantially ramp-shaped waveform.

67. The method of claim 65, further comprising the step of:

(D) initiating each ramp-shaped waveform cycle at an occurrence of a diversity transition.

68. The method of claim 59, further comprising the step of:

(D) receiving a baseband differential input signal across the first differential input node and the second differential input node.

69. A method for reducing a DC offset voltage in an input signal, comprising the steps of:

(A) coupling a capacitor between the input signal and an output signal; and

(B) varying the resistance of a variable resistor coupled between the output signal and a reference voltage according to a control signal.

70. The method of claim 69, wherein step (B) includes the step of:

(1) receiving a substantially ramp-shaped waveform cycle on the control signal.

71. The filter module of claim 70, wherein step (1) comprises the step of:

receiving an exponential waveform on the control signal.

72. The method of claim 71, wherein step (B) further comprises the steps of:

(2) causing the variable resistor to have a first resistance value at a first time during the ramp-shaped waveform cycle; and

(3) causing the variable resistor to have a second resistance value at a second time during the ramp-shaped waveform cycle.

73. The method of claim 72, wherein step (3) includes the step of:

causing the second resistance value to be greater than to the first resistance value.

74. The method of claim 72, wherein (3) includes the step of:

causing a cutoff frequency at the first time to be a higher frequency than a cutoff frequency at the second time.

75. The method of claim 74, further comprising the step of:

(C) acquiring a DC offset voltage in the capacitor more rapidly at the second time than at the first time.

76. The method of claim 70, wherein step (B) further includes the step of:

(2) receiving a second substantially ramp-shaped waveform cycle on the control signal.

77. The method of claim 76, wherein step (2) includes the step of:

causing an amplitude of the second substantially ramp-shaped waveform to be different from an amplitude of the first substantially ramp-shaped waveform.

78. The method of claim 76, further comprising the step of:

(C) initiating each ramp-shaped waveform cycle at an occurrence of a diversity transition.

79. The method of claim 69, further comprising the step of:

(C) receiving a baseband input signal.