Interface system

• US 20030225317A1
• Filed: 05/30/2003
• Published: 12/04/2003
• Est. Priority Date: 06/04/2002
• Status: Active Grant

• Current Assignee: Ascensia Diabetes Care Holdings AG (PHC Holdings Corporation)
• Original Assignee: Bayer Healthcare LLC (Bayer AG)
• Inventors: Schell, Robert D.
• Granted Patent: US 7,705,653 B2
• Time in Patent Office: Days
• US Class Current: 600/300
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

An interface system delivers an output signal having a first signal characteristic in response to first and second input signals having the first signal characteristic and a second, different signal characteristic. The interface system includes a signal input for receiving a first signal having a first signal characteristic and a second signal having a second signal characteristic which is different from the first signal characteristic, a detector circuit for detecting whether the signal at the input is the first signal or the second signal, and a translator circuit for translating either of the first signal or the second signal into the output signal.

Claims

1. An interface system for delivering an output signal having a said signal characteristic in response to first and second input signals having said first signal characteristic and a second signal characteristic different from said first signal characteristic, said interface system comprising:

a signal input for receiving a first signal having a first signal characteristic and a second signal having a second signal characteristic which is different from said first signal characteristic;

a detector circuit for detecting whether the signal at said input is said first signal or said second signal; and

a translator circuit for translating either of said first signal or said second signal into said output signal.

2. The system of claim 1 wherein said first and second signals comprise output signals of a metering device and wherein said output signals comprises a signal compatible with an input of a digital signal processor.

3. The system of claim 1 wherein said detector circuit is capable of recognizing a marking voltage characteristic of each of said first signal and said second signal.

4. The system of claim 3 wherein said detector circuit comprises a rectifier-capacitor circuit or a resistor-capacitor circuit.

5. The system of claim 1 wherein said translator includes a polarity setting circuit and a level setting circuit.

6. The system of claim 1 wherein said detector circuit includes a signal characteristic type detector circuit and a voltage level translator.

7. The system of claim 1 wherein said first signal is an RS-232 (EIA-232) output signal and said second signal is an open-collector output signal.

8. An interface method for delivering an output signal having a given signal characteristic in response to first and second input signals having said first signal characteristic and a second, signal characteristic different from said first signal characteristic, said method comprising:

receiving a first signal having a first signal characteristic and a second signal having a second signal characteristic which is different from said first signal characteristic;

detecting whether the signal at said input is said first signal or said second signal; and

translating either of said first signal or said second signal into said output signal.

9. The method of claim 8 wherein said first and second signals comprise output signals of a metering device and wherein said output signals comprises a signal compatible with an input of a digital signal processor.

10. The method of claim 8 wherein said detecting includes recognizing a marking voltage characteristic of each of said first signal and said second signal.

11. The method of claim 10 wherein said detecting uses a rectifier-capacitor circuit or a resistor-capacitor circuit.

12. The method of claim 8 wherein said translating includes polarity setting and level setting.

13. The method of claim 8 wherein said detecting includes detecting said signal characteristics and translating a voltage level of at least one of said first and second signals.

14. The method of claim 8 wherein said first signal is an RS-232 (EIA-232) output signal and said second signal is an open-collector output signal.

16. The interface system of claim 8 wherein said first and second signals comprise output signals of a metering device and wherein said output signals comprise a signal compatible with an input of a digital signal processor.

17. The interface system of claim 8 wherein said means for detecting includes means for recognizing a marking voltage characteristic of each of said first signal and said second signal.

18. The interface system of claim 10 wherein said means for detecting uses a rectifier-capacitor circuit or a resistor-capacitor circuit.

19. The interface system of claim 8 wherein said means for translating includes means for polarity setting and means for level setting.

20. The interface system of claim 8 wherein said means for detecting includes means for detecting said signal characteristics and means for translating a voltage level of at least one of said first and second signals.

21. The interface system of claim 8 wherein said first signal is an RS-232 (EIA-232) output signal and said second signal is an open-collector output signal.

15. An interface system for delivering an output signal having a given signal characteristic in response to first and second input signals having said first signal characteristic and a second signal characteristic different from said first signal characteristic, said system comprising:

means for receiving a first signal having a first signal characteristic and a second signal having a second signal characteristic which is different from said first signal characteristic;

means for detecting whether the signal at said input is said first signal or said second signal; and

means for translating either of said first signal or said second signal into said output signal.