Routing mechanisms in systems having multiple multi-processor clusters

• US 20030225938A1
• Filed: 05/28/2002
• Published: 12/04/2003
• Est. Priority Date: 05/28/2002
• Status: Active Grant

• Current Assignee: Sanmina-SCI Corporation
• Original Assignee: Newisys, Inc. (Sanmina-SCI Corporation)
• Inventors: Oehler, Richard R., Glasco, David Brian, Kota, Rajesh, Prasadh, Guru, Zeitler, Carl
• Granted Patent: US 7,281,055 B2
• Time in Patent Office: Days
• US Class Current: 713/375
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus

Abstract

A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.

Claims

1. A computer system comprising a plurality of processor clusters interconnected by a plurality of global links, each cluster including a plurality of local nodes and an interconnection controller interconnected by a plurality of local links, each cluster having routing information associated therewith for facilitating communication between the local processors and the interconnection controller via the local links, wherein the interconnection controller in each cluster is operable to map locally generated transmissions directed to others of the clusters to the global links, and remotely generated transmissions directed to the local nodes to the local links.

2. The computer system of claim 1 wherein the interconnection controller in each cluster is further operable to maintain at least one local routing table relating each of the local processors to at least one of the local links, and at least one global routing table relating each of the other clusters to at least one of the global links.

3. The computer system of claim 2 wherein the at least one local routing table comprises a directed routing table for facilitating directed transmissions between specified nodes on the local links, and a broadcast routing table for facilitating broadcast transmission to more than one node on the local links.

4. The computer system of claim 2 wherein the at least one global routing table comprises a directed routing table for facilitating directed transmissions between specified nodes on the global links, and a broadcast routing table for facilitating broadcast transmission to more than one node on the global links.

5. The computer system of claim 1 wherein the local links comprise point-to-point links.

6. The computer system of claim 1 wherein the global links comprise point-to-point links.

7. The computer system of claim 5 wherein the plurality of clusters comprises four clusters.

8. The computer system of claim 7 wherein the plurality of local nodes in each cluster comprises four local processors.

9. The computer system of claim 1 wherein the interconnection controller in each cluster is further operable to map locally generated address information to others of the clusters, and remotely generated address information to the local nodes.

11. The computer system of claim 1 wherein the interconnection controller in each cluster is further operable to map locally generated address information to others of the clusters, and remotely generated address information to the local nodes, and wherein the interconnection controller in each cluster is further operable to uniquely map selected ones of locally generated transactions directed to others of the clusters to a global transaction space, and remotely generated transactions directed to the local nodes to a local transaction space.

12. The computer system of claim 1 wherein selected ones of the local nodes comprise various combinations of corresponding units including any of at least one central processing unit, at least one memory controller, and at least one input/output interface.

10. The computer system of claim I wherein the interconnection controller in each cluster is further operable to uniquely map selected ones of locally generated transactions directed to others of the clusters to a global transaction space, and remotely generated transactions directed to the local nodes to a local transaction space.

13. In a computer system comprising a plurality of processor clusters interconnected by a plurality of global links, each cluster including a plurality of local nodes interconnected by a plurality of local links, a method for routing locally and remotely generated transmissions, the method comprising:

providing local routing information in each cluster relating each of the local nodes to at least one of the local links;

providing global routing information in each cluster relating each other cluster in the system to at least one of the global links;

mapping locally generated transmissions in each cluster directed to others of the clusters to the global links using the global routing information; and

mapping remotely generated transmissions directed to the local nodes to the local links using the local routing information.

14. An interconnection controller for use in a computer system comprising a plurality of processor clusters interconnected by a plurality of global links, each cluster including a plurality of local nodes and an instance of the interconnection controller interconnected by a plurality of local links, the interconnection controller comprising circuitry which is operable to map locally generated transmissions directed to others of the clusters to the global links, and remotely generated transmissions directed to the local nodes to the local links.

15. An integrated circuit comprising the interconnection controller of claim 14.

16. The integrated circuit of claim 15 wherein the integrated circuit comprises an application-specific integrated circuit.

17. At least one computer-readable medium having data structures stored therein representative of the interconnection controller of claim 14.

18. The at least one computer-readable medium of claim 17 wherein the data structures comprise a simulatable representation of the interconnection controller.

19. The at least one computer-readable medium of claim 18 wherein the simulatable representation comprises a netlist.

20. The at least one computer-readable medium of claim 17 wherein the data structures comprise a code description of the interconnection controller.

21. The at least one computer-readable medium of claim 20 wherein the code description corresponds to a hardware description language.

22. A set of semiconductor processing masks representative of at least a portion of the interconnection controller of claim 14.