Data modem

• US 20030225955A1
• Filed: 05/13/2002
• Published: 12/04/2003
• Est. Priority Date: 12/15/2000
• Status: Active Grant

• Current Assignee: Elbit Systems of America LLC (Elbit Systems Limited)
• Original Assignee: Innovative Concepts, Inc. (Elbit Systems Limited)
• Inventors: Long, Shawn, Smith, Troy, Smith, Gregory N., Woodward, Robert A., Weinberger, Barry P., Wexler, Michael M., Feldstein, Andy A.
• Granted Patent: US 6,839,792 B2
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: H04M 11/066 Telephone sets adapted for data transmision

Abstract

An improved data modem (IDM) and method includes a communication processor module, a mass storage module, a power converter module, and one or more DSP modules. The communication processor module utilizes commercial off-the-shelf components as well as electrically programmable logic devices (EPLD), which are programmed to provide a watchdog timer, programmable interrupt controller, flash page addressing, ISA bus decoder and controller, and various circuits and logic.

Claims

1. A data modem having a Communication Processor Module (CPM), wherein the CPM comprising:

a host central processing unit;

a host bus connected to the host central processing unit;

a system controller bridge connected to the central processing unit via the host bus;

a memory bus connected to the controller bridge;

a system memory connected to the controller bridge through the memory bus;

a peripheral component interconnect (PCI) bus connected to the controller bridge;

a peripheral component interconnect bridge interfaced with the controller bridge via the peripheral component interconnect bus;

flash memory connected to the peripheral component interconnect bridge; and

a first Erasable Programmable Logic Device (EPLD) connected to the interconnect bridge and the flash memory, wherein the first EPLD provides a plurality of electronic circuits.

2. The data modem as recited in claim 1, further comprising:

a serial communication controller connected to the peripheral component interconnect bus, wherein the communication controller controls synchronous and asynchronous communication ports; and

a second EPLD connected to the serial communication controller, wherein the second EPLD device provides a synchronous port fix so as to effect synchronous communication from the serial communication controller, and

wherein the first EPLD device provides an Industry Standard Architecture (ISA) bus decoder and controller, flash page addressing register, a programmable interrupt controller, and a watchdog timer.

3. The data modem as recited in claim 2, wherein the flash page addressing register in the first EPLD is a writable flash page register utilized to manipulate the flash memory so as to access more than 128 Kbytes of flash memory.

4. The data modem as recited in claim 2, wherein the programmable interrupt controller comprises seven asynchronous interrupt inputs and one asynchronous interrupt output, a 7-bit write/read interrupt mask register, and a 7-bit write/read interrupt pending register.

5. The data modem as recited in claim 4, wherein the 7-bit interrupt mask register is I/O mapped and word-readable, and wherein the 7-bit interrupt pending register is I/O mapped and word-readable/writable.

6. The data modem as recited in claim 2, wherein the first EPLD further comprises an IDM status level input so as to identify the system into which the CPM is inserted, wherein the system is either an Improved Data Modem or a Joint Combat Information Terminal.

7. The data modem as recited in claim 6, wherein the first EPLD further comprises a Ready Discrete bit and a Fail bit for providing system status that are I/O mapped, word-readable/writable, and resides at a predetermined address.

8. The data modem as recited in claim 2, wherein the ISA bus decoder comprises interface and control logic for a flash page register, a MIL-STD-1553B interface controller, the programmable interrupt controller, the watchdog timer, modem status, system status comprising a ready discrete and a fail status, an IDE reset inverter, and a hardware version register.

9. The data modem as recited in claim 8, wherein the MIL-STD-1553B interface controller provides a glueless interface between an ISA bus and a MIL-STD-1553B remote terminal.

10. The data modem as recited in claim 2, wherein the watchdog timer comprises a reset status bit which indicates that a watchdog reset has occurred when the bit is set, and wherein the watchdog timer generates a board reset in the event the timer is not software-reset.

11. The data modem as recited in claim 2, wherein the first EPLD comprises a word readable, I/O mapped version register residing at a predetermined address and containing a version number of the EPLD.

12. The data modem as recited in claim 2, wherein the first EPLD further comprises an Integrated Drive Electronics (IDE) reset inverter, wherein the reset inverter generates an additional reset signal for an external MSM IDE drive.

13. The data modem of claim 1, further wherein the host central processing unit is a Pentium-compatible microprocessor operable in real mode or protected mode.

14. The data modem as recited in claim 2, wherein the Push-to-Talk control comprises at least four programmable inverters for controlling Ground SIP PTT lines.

15. The data modem as recited in claim 2, wherein the second EPLD further comprises four general-purpose inverters for asserting additional PTT lines.

16. The data modem as recited in claim 2, wherein the EPLD further comprises IEEE-1394 buffer control for use to control buffers used for IEEE-1394 interface.

17. The data modem as recited in claim 1, further comprising:

a second EPLD connected to the peripheral component interconnect bus;

at least one serial communications controller connected to the peripheral component interconnect bus;

a local area network controller connected to the peripheral component interconnect bus; and

an IEEE-1394 backplane interface connected to the peripheral component interconnect bus,

wherein the flash memory is programmable with a BIOS and a boot kernel.

18. The data modem as recited in claim 17, wherein the at least one serial communication controller is a 4-channel communications controller.

19. The data modem as recited in claim 18, wherein the second EPLD comprises a synchronous port fix so as to allow the configuration of the at least one serial communication controller to initiate communication with an external radio source.

20. The data modem as recited in claim 19, wherein the synchronous port fix comprises:

a clock multiplexer having at least two inputs, an output and a selection signal input;

an internal clock source providing a clock signal to a first input of the multiplexer; and

a receive data delay connected to the output of the multiplexer, wherein the clock multiplexer provides a selectability between an external radio clock, which provides a clock signal to a second input of the multiplexer, and the internal clock source, wherein the receive data delay is used for realigning the phase of a multiplexed external radio clock with received data from an external radio source, and wherein the selection signal input is controlled by general purpose bits on the serial communication controller.

40. The CPM of claim 17, further comprising:

a Serial EEPROM interfaced with the local areal network controller, wherein the local area network controller is in compliance with Ethernet protocol.

41. The CPM of claim 40, further comprising:

a Joint Test Action Group interface for in-circuit-emulation.

54. The data modem as recited in claim 1, further comprising:

a controller peripheral connected to the peripheral component interconnect bus providing a plurality of signals for the local bus.

55. The data modem as recited in claim 1, further comprising:

a serial communication controller connected to the PCI bus, wherein the communication controller controls synchronous and asynchronous communication ports; and

,

a digitally controlled switch providing a synchronous operational mode fix so as to effect synchronous communication between the serial communication controller and one or more synchronous devices.

56. The data modem as recited in claim 1, wherein the first EPLD comprises a programmable interrupt controller, a local bus reset controller, and a regulator fault latch controller.

57. The data modem as recited in claim 2, wherein the programmable interrupt controller comprises eight asynchronous interrupt inputs and one asynchronous interrupt output, a 16-bit write/read interrupt mask register, and a 16-bit write/read interrupt pending register.

58. The data modem as recited in claim 57, wherein the 16-bit interrupt mask register is I/O mapped and word-readable/writeable, and the 16-bit interrupt pending register is I/O mapped and word-readable/writable.

59. The data modem as recited in claim 57, wherein the 16-bit interrupt pending register is positive and negative edge detectable and I/O mapped and word-readable/writable.

60. The data modem as recited in claim 57, wherein the 16-bit interrupt pending register comprises upper eight bits that are positive edge triggered and lower eight bits that are negative edge triggered, and wherein the interrupt pending register is I/O mapped and word-readable/writable.

61. The data modem as recited in claim 56, wherein the local bus reset controller in the first EPLD is a programmable reset controller providing at least four independent reset outputs, wherein the local bus reset controller effects the resetting of one or more module.

62. The data modem as recited in claim 61, further comprises a the local bus reset control register that is I/O mapped and word-writeable.

63. The data modem as recited in claim 62, wherein the local bus reset control register generates a pulse from a single I/O mapped word write.

64. The data modem as recited in claim 63, wherein the local bus reset pulse is bypassed by the reset signal of the controller peripheral connected to the PCI bus used to provide a plurality of signals for the local bus.

65. The data modem as recited in claim 56, wherein the regulator fault latch controller in the first EPLD is a hardware state-machine comprising of at least one input and one output used to reset a regulator, wherein the regulator is Low Dropout Regulator (LDO) for regulating Gunning Transistor Logic voltage of the CPM.

78. The data modem of claim 1, further comprising:

embedded auxiliary power source for maintaining an uninterruptible operation of the modem in case of a primary power fault.

79. The data modem of claim 78, wherein the auxiliary power comprises a hold-up capacitor, fuel cell, or a battery power cell.

80. The data modem as recited in claim 61, wherein, upon receiving a reset or interrupt signal from a module, at least the interrupting module is reset and a PCI re-enumeration is performed without resetting other modules or the entire data modem.

21. A method for initializing communication of a synchronous communication port device of a data modem, comprising the steps of:

providing an internal free-running clock signal;

providing an external clock signal;

selecting the free-running clock signal as a clocking signal for the synchronous communication port device;

configuring the communication port device;

deselect the free-running clock signal source and select the external clock signal as a clocking signal to the synchronous communication port device after the communication port is configured to thereby place the communication port device in an operating mode.

22. The method as recited in claim 21, wherein the external clock signal is provided from an external radio source, and the internal free-running clock signal is provided by the Communication Processor Module.

23. The method as recited in claim 21 further comprising the step of:

realigning the phase of the external clock signal with the phase of the data received from the external radio source.

24. A data modem having a synchronous communication port, comprising:

a synchronous serial communication controller having a clock slave mode;

a free-running clock signal source;

a selector having a selection input for selecting a clocking signal from the free-running clock signal source as the clocking signal for the serial communications controller during initialization of thereof or an external clocking source as the clocking signal for the synchronous serial communication controller after the initialization thereof; and

a delay circuit for delaying a received data so as to phase-match the receive data with the external clock signal selected from the selector.

25. A method for bootstrapping a communication processor module in a data modem having a watchdog timer, comprising the steps of:

clearing a reset status bit of the watchdog timer (setting status bit logic to

     0) upon cold bootstrapping the communication processor from a powered down state;

awaiting for a first predetermined time-out period by the watchdog to allow the communication processor time to initialize under a cold bootstrapping state or a watchdog reset state;

setting the reset status bit of the watchdog timer then resetting the communication processor module without resetting the status bit of the watchdog timer, if a software watchdog reset command is not issued from the communication processor to the watchdog timer within the first predetermined time-out period;

reducing the first predetermined time-out period of the watchdog timer to a second predetermined time-out period and issuing a software reset command to clear the watchdog timer;

continuing to issue software reset command to clear the watchdog timer a the second predetermined time-out period software resent command cannot be issued within the second predetermined time-out period; and

setting the reset status bit of the watchdog timer and resetting the communication processor module, if no subsequent software watchdog timer reset is issued within the second predetermined time-out period.

26. The method as recited in claim 25, wherein the first predetermined time-out period is about 90 seconds, and the second predetermine time-out period is about 5 seconds.

27. The method as recited in claim 25, wherein the step of awaiting for a first predetermined time out period to allow the communication processor time to initialize further comprising the step of:

providing a power-up reset signal for the communication processor from a power converter module, wherein the power-up reset signal is in a first logic state for predetermined period of time until the power converter module stabilizes, and the power-up reset signal is switched to a second logic state and remains in the second state until the power converter module is turned off.

28. The method as recited in claim 27, wherein the predetermined period of time is at least 105 ms.

29. A method for bootstrapping a communication processor module in a data modem in accordance with a BIOS thereon, comprising the steps of:

clearing a flash boot flag upon cold bootstrapping of the communication processor;

checking if the flash boot flag is set,

if the flash boot flag is set, then execute bootstrap instructions stored in flash memory,

if flash boot flag is not set, then check to see if configuration bits of the communication processor module are set;

if the configuration bits of the communication processor module are set, then execute bootstrap instructions stored in flash memory;

if the configuration bits of the communication processor module are not set, then execute an IDE primary master disk read;

determining if disk read was successful,

if disk read was not successful, then execute bootstrap instructions stored in flash memory,

if disk read was successful, then set flash boot flag, execute boot sector code, and execute disk operating system codes stored on disk.

30. The method of claim 29, further comprising the steps of:

determining whether the disk operating system is functioning within a predetermined period of time,

if disk operating system is not functioning, wherein a software watchdog reset command is not issued, a watchdog timer automatically resets a reset status bit and the communication processor module is reset.

31. The method of claim 30, further comprising the steps of:

determining whether the disk operating system is functioning within a predetermined period of time, wherein

if disk operating system is functioning, the clear the flash boot flag, execute CPM application code, control the watchdog timer until the CPM application code resumes control of the watchdog timer;

determining if the watchdog timer is receiving a software reset command to reset the watchdog timer every predetermined period of time (5 sec.)

continuing the execution of CPM application code, if the watchdog timer continues to receive a software reset command;

if the watchdog timer fails to receive a software reset command, then the watchdog sets a reset status bit and the communication processor module is reset.

32. A method for bootstrapping a communication processor module in a data modem, comprising the steps of:

executing BIOS routines;

executing a disk operating system;

executing an application program stored on a disk, wherein the application program comprises routine for periodically tickling a watchdog timer so as to inform the communication processor of the operational status of the application program; and

resetting the watchdog timer and the communication processor module in the even the watchdog timer fails to be tickled by the application program.

33. The method of claim 32, further comprising the steps of:

verifying if the disk operating system is invoked and functional within a predetermined time; and

setting the status bit of the watchdog timer and thereby resetting the communication processor module, if the disk operating system is not operational within the predetermined time.

34. The method of claim 33, further comprising the steps of:

executing bootstrapping routines stored in a flash memory, if a flash boot flag is set, the communication processor module is configured for flash boot, or execution of boot sector code and execution of disk operating system are not successful.

35. The method of claim 33, wherein the predetermined time is about 90 sec.

36. A method for configuring a clockless serial synchronous communication device in a data modem, comprising the steps of:

providing a temporary clock signal to the clockless serial synchronous communication device to thereby place the device in an initialization mode prior to communicating with an external radio source;

removing the temporary clock signal from the communication device after initialization is complete; and

providing an external clock signal to the communication device so as to allow communication with the external radio source.

37. The method of claim 36, further comprising the step of:

phase-matching the external clock signal and a data signal received from the external radio source.

38. A improved data modem, comprising:

a ruggedized housing comprising;

a backplane;

at least one communication processor module;

a mass storage module; and

a power converter module,

wherein the communication processor module comprises at least one EPLD providing a plurality of electronic circuits, and a Pentium-compatible microprocessor;

wherein the mass storage module comprises at least one solid-state drive; and

wherein each of the modules is compliant with Standard Electronic Module Form Factor E and are interfaced with one another via the backplane.

39. The improved data modem of claim 38, wherein the communication processor module is hardware compatible with Joint Combat Information Terminal.

51. The improved data modem of claim 38, wherein the mass storage module further comprises a 10/100 base-T Ethernet-compliant hub.

52. The improved data modem of claim 38, further comprising an Input/Output Module (IOM).

53. The improved data modem as recited in claim 38, wherein the backplane is a passive backplane providing an interconnection for a plurality of modules using a local bus architecture.

42. A method for bootstrapping a x86-based data modem, comprising the steps of:

providing a BIOS in a first page of a flash memory, and a backup boot kernel in subsequent pages of the flash memory;

executing BIOS instructions;

loading an Operating System from a hard drive into a system memory;

copying the backup boot kernel into the system memory and executing a backup operating system therein, if loading an Operating System from the hard drive is unsuccessful.

43. The method of claim 42, further comprising the steps of:

manipulating a memory page register so as to allow the first page of the flash memory containing the BIOS to be mapped into same physical addresses the system memory at the power-up of the data modem, or to allow the mapping subsequent pages of the flash memory containing the backup boot kernel into the same physical addresses of the system memory one page at a time in the event of loading the Operating System from a hard drive is unsuccessful.

44. The method of claim 43, further comprising the steps of:

copying the BIOS into the system memory after mapping the first page of the flash memory containing the BIOS into the same physical address of the system memory; and

copying the backup boot kernel into the system memory after mapping subsequent pages of Flash memory into the same physical address of the system memory when a hard disk boot failure occurs.

45. The method of claim 44, wherein the step of executing a backup operating system provided in the backup boot kernel comprises configuring the data modem to thereby provide a communication bus that is MIL-STD-1553B compliant and place the data modem in a degraded mode of operation.

46. A method for programming non-volatile memories in an x86-based data modem having a JTAG port using a in-circuit emulator, comprising the steps of:

resetting the communication system so as to place all components into a known state;

utilizing the emulator to seize control of a main processor of the communication system via the JTAG port;

configuring a first chipset and a second chipset, wherein a configured first chipset provides access to system dynamic random access memory, and a configured second chipset provides a PCI-to-ISA/IDE bridge function;

configuring the system synchronous dynamic random access memory;

load a first binary image and a first non-volatile memory burning program into the system dynamic random access memory by way of the first chipset;

programming the first non-volatile memory with the first binary image by executing the first memory burning program to effect the transfer of the first binary image from the system dynamic random access memory to the non-volatile memory through the second chipset.

47. The method of claim 46, further comprises the steps of:

loading a second binary image a second non-volatile memory burning program into the system dynamic random access memory by way of the first chipset;

programming the second non-volatile memory with the second binary image by executing the first memory burning program to effect the transfer of the second binary image from the system dynamic random access memory to the non-volatile memory through a local area network controller.

48. The method of claim 47, further comprising the steps of:

setting a breakpoint and an instruction pointer in the system dynamic random access memory to thereby pointing the instruction pointer to a first instruction location in the system dynamic random access memory and to provide a breakpoint where the non-volatile memory burning program terminates, wherein the first binary image is a BIOS.

49. The method a claim 46, wherein the step of programming the first non-volatile memory with the first binary image comprises programming a BIOS onto the first non-volatile memory.

50. The method a claim 47, wherein the step of programming the second non-volatile memory with the second binary image comprises programming the second non-volatile memory with Ethernet MAC IP address.

66. A method for power down interrupt in a data modem, comprising:

detecting a power fault using detecting means in a power converter module;

generating a power-down interrupt signal and providing the power-down interrupt signal to a communication processor module;

effecting a response from an application-level power-down interrupt handler routine;

wherein the handler routine performs the steps of;

writing volatile information to a non-volatile storage; and

signalling an operating system to backup buffered data in a volatile memory to a non-volatile memory.

67. The method of claim 66, after the step of providing the power-down interrupt signal to a communication processor module, further comprises the step of:

receiving the power-down interrupt signal by a secondary interrupt controller in the communication processor module;

detecting a state in the power-down interrupt signal and generating an interrupt signal to a programmable interrupt controller; and

providing an interrupt to a central processor vectored, via an interrupt descriptor table, to an interrupt request handler.

68. The method of claim 67, further comprising:

scanning interrupt status and mask registers for pending, embedded interrupts; and

calling a corresponding interrupt handling routine.

69. A Communication Processor Module (CPM), comprising:

detecting means for detecting a reset or an interrupt generated by another module, the detecting means utilizing an edge detection circuitry; and

interrogating means for checking the status of the module, from which a reset or interrupt signal is generated.

70. A data modem having an Input Output Module (IOM), wherein the IOM comprising:

a digital portion and an analog portion;

the digital portion comprises;

a digital signal processor (DSP);

a SDRAM bank connected to the DSP via an External Memory Interface (EMIF) bus;

a DSP-interface Field Programmable Logic Device (FPLD) interfaced to the DSP via the EMIF bus;

a watchdog implemented in a field programmable logic device;

a low-side driver interfaced to the DSP-interfaced FPLD; and

Low Voltage Differential Signaling (LVDS) drivers/receivers.

71. The IOM claim 70, wherein the analog portion comprises:

an Analog-Interface Field Programmable Logic Device (FPLD) connected to the LVDS drivers/receivers;

CODECS and analog circuitry connected to the analog-Interface FPLD;

ASK/FSK radio input/output circuits coupled to the CODECS and analog circuitry; and

radio control and status inputs/outputs coupled to the Analog-Interface FPLD.

72. The IOM of claim 70, wherein the DSP-interface FPLD comprises:

a multiplexer, controlled by a system reset, allowing signals to be routed to the low-side driver before the DSP-interface FPLD is loaded with operational code

73. The IOM of claim 70, wherein the watchdog comprises a counter and an associated software-accessible register, and wherein the watchdog is initialized by a software and operates under hardware control.

74. The IOM of claim 73, wherein the software-accessible register is accessed by periodically the software so as to reset the counter and to prevent the counter from reaching a terminal count during normal operation, and wherein the IOM is reset if the terminal count is reached.

75. The IOM of claim 70, wherein power is removed from the DSP and the SDRAM during a reset so as to force the SDRAM to reset and to allow the interface between the DSP and the SDRAM to operate properly.

76. The IOM of claim 72, wherein, using the multiplexer, the low-side driver is initialized before the DSP-interfaced FPLD is loaded with operational code.

77. The IOM of claim 71, further comprises a master clock connected to the CODECS, wherein a sampling phase of the CODECS is adjustable by increasing or decreasing the frequency of the master clock thereby effecting a shift in the sampling phase.