Software command sequence for optimized power consumption

• US 20030225987A1
• Filed: 05/28/2002
• Published: 12/04/2003
• Est. Priority Date: 05/28/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie Fariborz
• Granted Patent: US 7,251,711 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

Power consumption by a memory device is optimized by maintaining data input buffers in an off state until a command sequence containing a write command is received by the memory. A software command sequence is provided to the memory device where the software command sequence was constructed by generating a command sequence of n cycles and providing valid data in each cycle in which a write command is generated after a m^th cycle of the command sequence, where m is less than n. The data input buffers are returned to an off state upon completion of a program or erase operation defined in the received command sequence.

Claims

1. A method for writing to a memory device comprising:

generating a command sequence of n cycles; and

providing valid data in each cycle in which a write command is generated after a m^th cycle of the command sequence, m being less than n.

2. The method of claim 1, wherein providing valid data in each cycle in which a write command is generated after a m^th cycle of the command sequence occurs for m equal to one.

3. The method of claim 1, wherein providing valid data in each cycle in which a write command is generated after a m^th cycle of the command sequence is performed with the m^th cycle being a first cycle containing a write command.

4. The method of claim 1, wherein providing valid data in each cycle in which a write command is generated after a m^th cycle of the command sequence is performed with the m^th cycle being a second cycle containing a write command.

5. The method of claim 1, wherein the method further includes providing arbitrary data on a first cycle through the m^th cycle.

6. The method of claim 1, wherein generating a command sequence of n cycle s includes gene rating a command code to program or erase specified portions of the memory device.

7. A method for writing to a memory device comprising:

generating a command sequence of n cycles; and

generating valid data provided for a first plurality of data input buffers in each cycle in which a write command is generated after a m^th cycle of the command sequence, m being less than n.

8. The method of claim 7, wherein the method further includes generating valid data provided for a second plurality of data input buffers on a first cycle containing a write command of the command sequence.

9. The method of claim 7, wherein the method further includes generating valid data provided for a second plurality of data input buffers on a k^th cycle of the command sequence, k being less than m, the k^th cycle containing a write command.

10. A method for writing to a memory device comprising:

generating a command sequence of n cycles; and

generating valid data provided for T data input buffers, the T data input buffers grouped into R sets of data input buffers, wherein valid data is provided for a j^th set of the R sets of data input buffers on a m_j^th cycle of the command sequence, 1≦

j≦

R and 1≦

m_j≦

n, the m_j^th cycle containing a write command.

11. The method of claim 10, wherein generating valid data provided for T data input buffers includes generating valid data provided for T data input buffers, T equal to 32.

12. A method for writing to a memory device comprising:

receiving a write request; and

generating a command sequence of n cycles in response to the write request; and

providing valid data in each cycle in which a write command is generated after a m^th cycle of the command sequence, m being less than n.

13. The method of claim 12, wherein providing valid data in each cycle in which a write command is generated after a m^th cycle of the command sequence occurs for m equal to one.

14. The method of claim 12, wherein providing valid data in each cycle in which a write command is generated after a m^th cycle of the command sequence is performed for the m^th cycle being a first cycle containing a write command.

15. The method of claim 12, wherein the method further includes providing arbitrary data on a first cycle through the m^th cycle.

16. A method for writing to a memory device comprising:

receiving a write request;

generating a command sequence of n cycles in response to the write request; and

providing valid data in each cycle in which a write command is generated after a m^th cycle of the command sequence, m being less than n, wherein the valid data is provided for a first plurality of data input buffers.

17. The method of claim 16, wherein the method further includes providing arbitrary data on a first cycle through the m^th cycle.

18. The method of claim 16, wherein the method further includes providing valid data for a second plurality of data input buffers on a first cycle of the command sequence.

19. The method of claim 16, wherein the method further includes providing valid data for a second plurality of data input buffers on a first cycle of the command sequence containing a write command.

20. The method of claim 16, wherein the method further includes generating valid data provided for a second plurality of data input buffers on a k^th cycle of the command sequence, k being less than m, the k^th cycle containing a write command.

21. The method of claim 20, wherein the method further includes generating valid data provided for a third plurality of data input buffers on the j^th cycle of the command sequence, m<

j<

n, the j^th cycle containing a write command.

22. A method of operating a memory device comprising:

receiving a command sequence of n cycles;

detecting a write command and a valid address in the m^th cycle of the command sequence, m<

n; and

placing data input buffers into an on state in response to detecting a write command and a valid address in the m^th cycle of the command sequence.

23. The method of claim 22, wherein detecting a write command and a valid address in the m^th cycle of the command sequence occurs with m equal to one.

24. The method of claim 22, wherein detecting a write command and a valid address in the m^th cycle of the command sequence is performed for the m^th cycle being a first cycle containing a write command.

25. The method of claim 22, wherein receiving a command sequence of n cycles includes receiving a command sequence having a command code to program or erase specified portions of the memory device.

26. The method of claim 22, wherein the method further includes:

monitoring the n cycles;

determining if information provided in each cycle matches a predetermined criteria;

performing a program operation or an erase operation as determined from the information provided in the n cycles; and

placing the data input buffers into an off state at the completion of performing a program operation or an erase operation as determined from the information provided in the n cycles.

27. The method of claim 26, wherein the method further includes, for a data input buffer selected to be in a continually on state, maintaining the data buffer in an on state at the completion of performing a program operation or an erase operation as determined from the information provided in the n cycles.

28. The method of claim 26, wherein the method further includes monitoring a address provided in each cycle and prohibiting a write or erase operation if the monitored address differs from a predetermined address for each cycle.

29. The method of claim 28, wherein the method further includes taking the predetermined address in a cycle containing data to be programmed or a code commencing an erase operation to be the address to be programmed or erased.

36. The method of claim 24, wherein placing T data input buffers in an on state includes having at least one j^th set of data input buffers continually in an on state.

37. The method of claim 24, wherein detecting a first cycle of a command sequence comprises detecting a first cycle containing a write command in the command sequence.

30. A method of operating a memory device comprising:

receiving a command sequence of n cycles;

detecting a write command and a valid address in the m^th cycle of the command sequence, m<

n; and

placing a first plurality of data input buffers into an on state in response to detecting a write command and a valid address in the m^th cycle of the command sequence.

31. The method of claim 30, wherein detecting a write command and a valid address in the m^th cycle of the command sequence includes using an arbitrary address as a valid address associated with a first write command of the command sequence.

32. The method of claim 30, wherein the method further includes maintaining a second plurality of data input buffers in the on state continually.

33. The method of claim 30, wherein the method further includes placing a second plurality of data input buffers into an on state on a k^th cycle of the command sequence in response to detecting a first cycle of a command sequence, k being less than m.

34. The method of claim 30, wherein the method further includes placing a second plurality of data input buffers into an on state on a k^th cycle of the command sequence in response to detecting a first cycle containing a write command, k being less than m.

35. A method of operating a memory device comprising:

receiving a command sequence of n cycles;

detecting a first cycle of a command sequence; and

placing T data input buffers in an on state, the T data input buffers grouped into R sets of data input buffers, wherein a j^th set of the R sets of data input buffers is placed in an on state beginning for a m_j^th cycle of the command sequence for all j^th sets, 1≦

j≦

R and 1≦

m_j≦

n.

38. A memory device comprising:

control circuitry; and

data input buffers configured in an off state, the data input buffers switchable to an on state responsive to the control circuitry detecting an externally generated command sequence of n cycles.

39. The memory device of claim 38, wherein the control circuitry is configured to place the data input buffers into an off state upon completing an execution of an operation defined by the command sequence.

40. The memory device of claim 38, wherein the control circuitry is configured to identify the first m cycles of the command sequence, m<

n.

41. The memory device of claim 40, wherein the control circuitry is further configured to detect commands and addresses associated with the command in each cycle of the command sequence.

42. The memory device of claim 38, wherein the control circuitry is configured to place the data input buffers in an on state in response to detecting a first m cycles of the command sequence of n cycles.

43. The memory device of claim 42, wherein the control circuitry is further configured to detect a first m cycles of a command sequence of n cycles by determining the presence of at least one write command with a predetermined address in the first m cycles of the command sequence.

44. The memory device of claim 42, wherein m equals one.

45. The memory device of claim 42, wherein the m^th cycle is a first cycle containing a write command in the command sequence.

46. The memory device of claim 38, wherein the memory device is a non-volatile memory.

47. The memory device of claim 38, wherein the memory device is a synchronous Flash memory.

48. A memory device comprising:

control circuitry; and

a first plurality of data input buffers configured in an off state, wherein the first plurality of data input buffers are placed in an on state in response to the control circuitry detecting a first m cycles of an externally generated command sequence of n cycles, m<

n.

49. The memory device of claim 48, further including a second plurality of data input buffers continuously configured in an on state.

50. The memory device of claim 48, further including a second plurality of data input buffers configured in an off state, wherein the second plurality of data input buffers are placed in an on state on a k^th cycle of the command sequence in response to the control circuitry detecting a first cycle of the externally generated command sequence of n cycles, k<

n.

51. The memory device of claim 48, further including a second plurality of data input buffers configured in an off state, wherein the second plurality of data input buffers are placed in an on state on a k^th cycle of the command sequence in response to the control circuitry detecting a first cycle of the externally generated command sequence containing a write command.

52. A memory device comprising:

control circuitry; and

T data input buffers configured in an off state, the T data input buffers grouped into R sets of data input buffers, wherein a j^th set of the R sets of data input buffers is placed in an on state beginning for a m_j^th cycle of an externally generated command sequence of n cycles in response to the control circuitry detecting a reception of a command sequence for all j^th sets, 1≦

j≦

R and 1≦

m_j≦

n.

53. The memory device of claim 52, wherein the control circuitry detects a reception of a command sequence by detecting a first write command.

54. The memory device of claim 52, wherein at least one j^th set of data input buffers is continually in an on state.

55. The memory device of claim 52, wherein the control circuitry places the T data input buffers in an off state upon completion of a program or erase operation.

56. The memory device of claim 55, wherein a j^th set designated as a data input buffer in a continually on state remains in an on state upon completion of the program or erase operation.

57. A memory module comprising:

input ports for receiving a write request;

a load command unit coupled to the input ports for converting the received write request into a command sequence of n cycles; and

output ports coupled to the load command unit for directing the command sequence to a memory device.

58. The memory module of claim 57, where the load command unit is configured to generate a write command with associated valid data during a m^th cycle in the n cycle command sequence after generating a cycle with a first write command, wherein m is less than n.

59. The memory module of claim 58, wherein the load command unit is configured to generate arbitrary data in each cycle where a write command is generated before generating the m^th cycle in the n cycle command sequence.

60. The memory module of claim 58, wherein the load command unit is configured to generate valid data for each cycle containing a write command after the m^th cycle.

61. The memory module of claim 57, where the load command unit is configured to generate a write command with associated valid data during a m^th cycle in the n cycle command sequence, the m^th cycle is the first cycle in the n cycle command sequence containing a write command, wherein 1<

m<

n.

62. An information handling system comprising:

a processor;

a load command unit coupled to the processor for receiving a write request form the processor; and

a memory device coupled to the load command unit, wherein the load command unit is configured to generate a command sequence of n cycles to the memory device with valid data provided in each cycle containing a write command after a m^th cycle, m being less than n.

63. The information handling system of claim 62, wherein the load command unit is further configured to generate the command sequence of n cycles to the memory device in response to the write request from the processor.

64. The information handling system of claim 62, wherein the memory device comprises data input buffers configured in an off state until the memory device determines the reception of a command sequence.

65. The information handling system of claim 64, wherein the memory device is configured to place the data input buffers in an on state upon detecting a first cycle of the n cycle command sequence containing a write command.

66. The information handling system of claim 64, wherein the memory device is configured to place the data input buffers in an off state upon completing an operation defined in the command sequence.

67. An information handling system comprising:

a processor; and

a memory device coupled to the processor, the memory device comprising;

control circuitry; and

data input buffers configured in an off state, the data input buffers switchable to an on state responsive to the control circuitry detecting an externally generated command sequence of n cycles.

68. The information handling system of claim 67, wherein the control circuitry is configured to place the data input buffers into an off state upon completing an execution of an operation defined by the command sequence.

69. The information handling system of claim 67, wherein the control circuitry is configured to identify the first m cycles of the command sequence, m<

n.

70. The information handling system of claim 69, wherein the control circuitry is further configured to detect addresses associated with a command in each cycle of the command sequence.

71. The information handling system of claim 67, wherein the control circuitry is configured to place the data input buffers in an on state in response to detecting a first m cycles of the command sequence of n cycles.

72. The information handling system of claim 71, wherein the control circuitry is further configured to detect a first m cycles of a command sequence of n cycles by determining the presence of at least one write command with a predetermined address in the first m cycles.

73. The information handling system of claim 71, wherein m equals one.

74. The information handling system of claim 71, wherein the m^th cycle is a first cycle containing a write command in the command sequence.

75. A data signal for a memory device embodied in a set of electrical signals comprising:

a sequence of n cycles, each cycle comprising;

a first data portion containing data representing a command;

a second data portion containing data representing a memory address; and

a third data portion containing data representing data to be stored in the memory or a code for performing an operation, wherein the sequence of n cycles is a command sequence containing valid data in the third data portion for each cycle containing a write command in the first data portion beginning in a m^th cycle, m<

n, wherein the command sequence contains arbitrary data in the third data portion for each cycle containing a write command in the first data portion prior to the m^th cycle.

76. The data signal of claim 75, wherein n equals eight.

77. The data signal of claim 75, wherein m equals four.

78. The data signal of claim 75, wherein m equals six.

79. The data signal of claim 75, wherein each cycle contains a fourth data portion containing data representing a bank address.

80. The data signal of claim 79, wherein valid data representing a bank address is provided in the second cycle and subsequent cycles of the n cycle sequence, the valid data remaining constant in the second and subsequent cycles.