Semiconductor device having\ gate with negative slope and method for manufacturing the same

• US 20030227055A1
• Filed: 01/13/2003
• Published: 12/11/2003
• Est. Priority Date: 06/05/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Nae-in, Rhee, Hwa-sung, Kim, Ki-chul, Bae, Geum-jong, Kim, Sang-su, Lee, Jung-il
• Granted Patent: US 6,878,580 B2
• Time in Patent Office: Days
• US Class Current: 257/346
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/2807 the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape

Abstract

A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a gate dielectric layer formed on the semiconductor substrate; and

a poly-SiGe gate, formed on the gate dielectric layer, wherein a bottom of the gate is narrower than a top of the gate by having sloping sides.

2. The semiconductor device of claim 1, wherein the bottom of the gate is narrower than the top of the gate by about 10 nm to about 80 nm.

3. The semiconductor device of claim 1, wherein the Ge density is greater at the bottom of the gate than at the top of the gate, and the Ge density decreases linearly from the bottom of the gate toward the top of the gate.

4. The semiconductor device of claim 3, wherein the Ge density ranges from about 30 at % to about 50 at % at the bottom of the gate and from 0 to about 10 at % at the top of the gate.

5. The semiconductor device of claim 1, wherein the Ge density in the gate is uniform throughout the entire gate.

6. The semiconductor device of claim 1, wherein the sloping sides are negatively sloped.

7. A method for manufacturing a semiconductor device comprising:

(a) forming a gate dielectric layer on a semiconductor substrate;

(b) forming a silicon seed layer on the gate dielectric layer;

(c) forming a poly-SiGe layer by flowing Si source gas and Ge source gas on the seed layer at substantially the same time;

(d) forming a gate whose bottom is narrower than its top; and

(e) forming a source/drain region on the semiconductor device at both sides of the gate by implanting impurities on the resultant structure on which the gate is formed.

8. The method of claim 7, wherein the poly-SiGe layer having a Ge density gradient is created by decreasing the amount of the Ge source gas.

9. The method of claim 7, wherein the step of forming the gate further includes patterning the poly-SiGe layer using the characteristic that a portion of the poly-SiGe layer with a greater Ge density etches at a faster rate than the portion of the poly-SiGe layer with a lower Ge density.

10. The method of claim 7, wherein the step of forming the gate whose bottom is narrower than its top is due to negatively sloping sides.

11. The method of claim 7, wherein the seed layer is formed of polycrystalline silicon or amorphous silicon.

12. The method of claim 7, further comprising forming a silicon capping layer on the poly-SiGe layer after step (c) is completed.

13. The method of claim 7, wherein the Ge density in the poly-SiGe layer formed in step (c) is greater at the bottom of the gate than at the top of the gate and decreases linearly toward the top of the gate.

14. The method of claim 13, wherein the Ge density in the gate ranges from about 30 to about 50 at % at the bottom of the gate, and ranges from 0 to about 10 at % at the top of the gate.

15. The method of claim 7, further comprising performing a thermal process on the resultant structure on which the gate is formed to make the germanium density uniform throughout the entire gate.

16. The method of claim 7, wherein step (d) further comprises:

(d-1) pre-etching using gas including CF₄ and Cl₂;

(d-2) main-etching using gas including HBr, Cl₂, He and O₂; and

(d-3) over-etching using gas HBr, Cl₂, He, O₂ and N₂.