Apparatus and method for determining leakage current between a first semiconductor region and a second semiconductor region to be formed therein

• US 20030227293A1
• Filed: 06/11/2002
• Published: 12/11/2003
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Delphi Technologies Ip Limited (BorgWarner Incorporated)
• Original Assignee: Dean M. Dahlgnist, Diane W. Sidner, John R. Fruth
• Inventors: Sidner, Diane W., Dahlgnist, Dean M., Fruth, John R.
• Granted Patent: US 6,836,134 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

An apparatus and method for measuring leakage current between a first semiconductor region and a second semiconductor region to be formed therein includes a system for measuring surface minority carrier leakage within the first semiconductor region. A correlation is established between surface minority carrier lifetime in the first semiconductor region and leakage current between the first and second semiconductor regions, and in one embodiment a surface minority carrier lifetime threshold is designated based on this correlation. Leakage current between the first and second regions is acceptable if the measured surface minority carrier lifetime is greater than this threshold. In an alternate embodiment, a leakage current threshold is established, and the measured surface minority carrier leakage is converted via the correlation to a measured leakage current. Leakage current between the first and second regions is acceptable in this embodiment if the measured leakage current is less than the leakage current threshold.

Claims

1. A method of determining leakage current between a first semiconductor region and a second semiconductor region to be subsequently formed therein, the method comprising the steps of:

correlating surface minority carrier lifetime in the first semiconductor region to leakage current between the first and second semiconductor regions;

based on the correlation between surface minority carrier lifetime and leakage current, establishing a surface minority carrier lifetime threshold;

measuring surface minority carrier lifetime in the first semiconductor region; and

determining that the leakage current between the first and second semiconductor regions is acceptable if the measured surface minority carrier lifetime is greater than the surface minority carrier lifetime threshold.

2. The method of claim 1 wherein the first and semiconductor regions form at least a portion of a semiconductor wafer.

3. The method of claim 1 wherein the first semiconductor region is an epitaxial semiconductor region and the second semiconductor region is diffused into the epitaxial semiconductor region.

4. The method of claim 3 wherein the first semiconductor region is an epitaxial semiconductor region and the second semiconductor region is implanted into the epitaxial semiconductor region.

5. The method of claim 1 wherein the first semiconductor region is an N-type semiconductor region and the second semiconductor region is a P-type semiconductor region.

6. The method of claim 1 wherein the first semiconductor region is a P-type semiconductor region and the second semiconductor region is an N-type semiconductor region.

7. The method of claim 2 further including the step of allowing continued fabrication of the semiconductor wafer if the leakage current between the first and second semiconductor regions is acceptable.

8. The method of claim 2 further including the step of scrapping the semiconductor wafer if the measured surface minority carrier lifetime is less than the surface minority carrier lifetime threshold.

9. A method of determining leakage current between a first semiconductor region and a second semiconductor region to be subsequently formed therein, the method comprising the steps of:

establishing a leakage current threshold;

correlating surface minority carrier lifetime in the first semiconductor region to leakage current between the first and second semiconductor regions;

measuring surface minority carrier lifetime in the first semiconductor region;

based on the correlation between surface minority carrier lifetime and leakage current, converting the measured surface minority carrier lifetime to a measured leakage current; and

determining that the leakage current between the first and second semiconductor regions is acceptable if the measured leakage current is less than the leakage current threshold.

10. The method of claim 9 wherein the first and semiconductor regions form at least a portion of a semiconductor wafer.

11. The method of claim 9 wherein the first semiconductor region is an epitaxial semiconductor region and the second semiconductor region is diffused into the epitaxial semiconductor region.

12. The method of claim 11 wherein the first semiconductor region is an epitaxial semiconductor region and the second semiconductor region is implanted into the epitaxial semiconductor region.

13. The method of claim 9 wherein the first semiconductor region is an N-type semiconductor region and the second semiconductor region is a P-type semiconductor region.

14. The method of claim 9 wherein the first semiconductor region is a P-type semiconductor region and the second semiconductor region is an N-type semiconductor region.

15. The method of claim 10 further including the step of allowing continued fabrication of the semiconductor wafer if the leakage current between the first and second semiconductor regions is acceptable.

16. The method of claim 10 further including the step of scrapping the semiconductor wafer if the measured leakage current is greater than the leakage current threshold.

17. Apparatus for determining leakage current between a first semiconductor region and a second semiconductor region to be subsequently formed therein, the apparatus comprising:

a memory having stored therein a surface minority carrier lifetime threshold based on a correlation between surface minority carrier lifetime in the first semiconductor region and leakage current between the first and second semiconductor regions;

a probe configured to interface with the first semiconductor region and produce one or more signals relating to surface minority carrier lifetime therein; and

a computer responsive to the one or more signals to determine a measured surface minority carrier lifetime in the first semiconductor region, the computer determining that the leakage current between the first and second semiconductor regions is acceptable if the measured surface minority carrier lifetime is greater than the surface minority carrier lifetime threshold and otherwise determining that the leakage current is unacceptable.

18. The apparatus of claim 17 wherein the first semiconductor region is one of an N-type semiconductor material and a P-type semiconductor material, and the second semiconductor region is the other of an N-type semiconductor material and a P-type semiconductor material;

and wherein the first and second semiconductor regions form at least a portion of a semiconductor wafer.

19. Apparatus for determining leakage current between a first semiconductor region and a second semiconductor region to be subsequently formed therein, the apparatus comprising:

a memory having stored therein a leakage current threshold and a correlation between surface minority carrier lifetime in the first semiconductor region and leakage current between the first and second semiconductor regions;

a probe configured to interface with the first semiconductor region and produce one or more signals relating to surface minority carrier lifetime therein; and

a computer responsive to the one or more signals to determine a measured surface minority carrier lifetime in the first semiconductor region and to convert the measured surface minority carrier lifetime to a measured leakage current based on the correlation therebetween, the computer determining that the leakage current between the first and second semiconductor regions is acceptable if the measured leakage current is less than the leakage current threshold and otherwise determining that the leakage current is unacceptable.

20. The apparatus of claim 19 wherein the first semiconductor region is one of an N-type semiconductor material and a P-type semiconductor material, and the second semiconductor region is the other of an N-type semiconductor material and a P-type semiconductor material;

and wherein the first and second semiconductor regions form at least a portion of a semiconductor wafer.