Semiconductor memory device having an array voltage control circuit constructed with a plurality of feedback loops

• US 20030227812A1
• Filed: 04/01/2003
• Published: 12/11/2003
• Est. Priority Date: 06/08/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Doo-Young, Kim, Byung-Chul
• Granted Patent: US 6,775,199 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

The invention discloses a semiconductor memory device having an array voltage control circuit constructed with a plurality of feedback loops. In order to maintain constant the array voltage used for a single memory cell array region the plurality of feedback loops dividedly connect to a power line structure covering the memory cell array region, resulting in a reduction in the load to be taken by the output of feedback amplifiers to thereby achieve stable array voltage control operations.

Claims

1. A semiconductor memory device including an array voltage control circuit, comprising:

a memory cell array;

a power line structure covering the memory cell array; and

a plurality of feedback loops coupled to the power line structure, the feedback loops being adapted to maintain constant a level of an array voltage by providing the array voltage to the power line structure through a plurality of paths.

2. The device of claim 1 wherein the power line structure is a mesh.

3. A semiconductor memory device, comprising:

a memory cell array adapted to receive an array voltage;

a mesh power supply structure corresponding to the memory cell array and adapted to supply the array voltage to the memory cell array;

a plurality of feedback buses connected to the mesh power supply structure;

a plurality of feedback circuits, each feedback circuit being adapted to compare an array voltage corresponding to a predetermined portion of the mesh power supply structure fed back through a corresponding feedback bus to a reference array voltage; and

a plurality of array voltage drivers adapted to supply the array voltage to the mesh power supply structure responsive to the plurality of feedback circuits.

4. The device of claim 3 wherein the mesh power supply structure is a single mesh.

5. The device of claim 3

wherein the mesh power supply structure includes a plurality of divisional supply liners;

and

wherein each of the plurality of feedback circuits is coupled to one of the divisional supply liners.

6. A semiconductor memory device, comprising:

a memory cell array adapted to receive an array voltage;

a mesh power supply structure divided into a plurality of divisional liners, each liner adapted to supply a predetermined portion of the memory cell array with the array voltage;

a plurality of feedback buses corresponding to the plurality of divisional liners;

a plurality of feedback circuits corresponding to the plurality of feedback buses, each feedback circuit being adapted to compare an array voltage received from a corresponding divisional liner to a reference array voltage; and

a plurality of array voltage drivers adapted to supply the array voltage to a corresponding divisional liner responsive to a corresponding feedback circuit.

7. An array voltage control circuit for controlling an array voltage applied to a memory cell array in a semiconductor memory device, comprising:

a plurality of feedback loops adapted to control the array voltage delivered to a predetermined portion of the memory cell array; and

a plurality of voltage drivers adapted to provide the array voltage to corresponding portions of the memory cell array responsive to the plurality of feedback loops.

8. The device of claim 7 wherein the plurality of voltage drivers delivers the array voltage to predetermined portions of the memory cell array through a single power mesh.

9. The device of claim 7 wherein the plurality of voltage drivers delivers the array voltage to the predetermined portions of the memory cell array through divisional liners included in a power supply mesh.

10. The device of claim 7 wherein the feedback loops are located in or out of the memory cell array.

11. A semiconductor memory device, comprising:

a power supply mesh associated with a memory cell array; and

a plurality of feedback circuits adapted to control supply of an array voltage to predetermined portions of the memory cell array through the power supply mesh.

12. The semiconductor memory device of claim 12 wherein the power supply mesh includes a plurality of divisional liners, each divisional liner being associated with a particular portion of the memory cell array.

13. The semiconductor memory device of claim 12 wherein each feedback circuit comprises:

a feedback bus; and

a feedback amplifier adapted to compare an array reference voltage to an array voltage received from the feedback bus.

14. The semiconductor memory device of claim 12 including a plurality of voltage driver circuits, each voltage driver circuit being adapted to provide the array voltage to the predetermined portions of the memory cell array responsive to corresponding feedback circuits.