Active polyphase inverter filter for quadrature signal generation

• US 20030227983A1
• Filed: 06/04/2003
• Published: 12/11/2003
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Rawlins, Michael W., Milne, Gregory L., Rawlins, Gregory S.
• Granted Patent: US 7,321,640 B2
• Time in Patent Office: Days
• US Class Current: 375/302
• CPC Class Codes: H04L 27/364 Arrangements for overcoming imperfections in the modulator, e.g. quadrature error or unbalanced I and Q levels

Abstract

A quadrature signal generator receives a differential input signal and generates quadrature output signals that are 90 degrees out-of-phase with each other. The quadrature generator includes a coarse stage and a plurality of refinement stages. The coarse stage generates quadrature signals that may have some phase error, and the refinement stages process the quadrature signals to reduce any phase error. The refinement stages receive quadrature signals from the output of the coarse stage, and processes the quadrature signals to reduce the phase errors. The coarse stage and the refinement stages are configured using delay circuits that can be implemented with inverter circuits, such as, for example, CMOS inverter circuits. In the refinement stages, corresponding outputs of the delay stages are averaged together to reduce the quadrature phase error.

Claims

1. A quadrature signal generator, comprising:

a coarse stage for generating output signals that have substantially a quadrature phase relationship, said coarse stage having at least one 90/180 delay circuit having a first set of inverters and a second set of inverters, said second set of inverters having an approximate delay of 90 degrees relative to said first set of inverters; and

at least one refinement stage for refining said quadrature phase relationship of said output signals from said coarse stage, said refinement stage having at least one 0/180 delay circuit, said 0/180 delay circuit having a third series of inverters and a fourth series of inverters, said fourth series of inverters having an approximate delay of 180 degrees relative to said third series of inverters.

2. The quadrature signal generator of claim 1, wherein said at least one refinement stage comprises four refinement stages, each of said four refinement stages further refining said 90 degree phase relationship between said output signals.

3. The quadrature signal generator of claim 1, wherein said at least one refinement stage includes a second 90/180 delay circuit.

4. The quadrature signal generator of claim 1, wherein at least one of said first, second, third, and fourth series of inverters are CMOS inverters.

5. A quadrature signal generator, comprising:

a coarse stage capable of generating quadrature output signals that have substantially a 90-degree phase relationship based on a differential input signal; and

at least one refinement stage for refining said 90 degree phase relationship of said output signals from said coarse stage, said refinement stage having,

a plurality of 0/180 delay circuits each receiving a corresponding quadrature output signal and having a 0-degree output and a 180-degree output, wherein a 0-degree output of a first 0/180 delay circuit is coupled to a 180 degree output of a second 0/180 delay circuit, and

a plurality of 90/180 delay circuits having inputs coupled to corresponding 0-degree outputs of said plurality of 0/180 delay circuits, wherein a 90-degree output of a first 90/180 delay circuit is coupled to a 180 degree output of a second 90/180 delay circuit.

6. The quadrature signal generator of claim 5, wherein said first 0/180 delay circuit and said second 0/180 delay circuit are separated by a third 0/180 delay circuit.

7. The quadrature signal generator of claim 5, wherein said first 0/180 delay circuit is a m^th delay circuit in said plurality of 0/180 delay circuits, and wherein said second 0/180 delay circuit is a (m+2)^th delay circuit in said plurality of 0/180 delay circuits.

8. The quadrature signal generator of claim 5, wherein said first 90/180 delay circuit is adjacent to said second 90/180 delay circuit.

9. The quadrature signal generator of claim 5, wherein said first 90/180 delay circuit is a m^th delay circuit in said plurality of 90/180 delay circuits, and wherein said second 90/180 delay circuit is a (m+1)^th delay circuit in said plurality of 90/180 delay circuits.

10. The quadrature signal generator of claim 5, wherein each 0/180 delay circuit includes:

a first set of inverters, that have an input that receives said corresponding quadrature output signal and an output connected to said 0 degree output of said 0/180 delay circuit; and

a second set of inverters, that have an input that receives said corresponding quadrature output signal and an output connected to said 180 degree output of said 0/180 delay circuit;

wherein second set of inverters have an approximate delay of 180 degrees relative said first set of inverters.

11. The quadrature signal generator of claim 5, wherein said O-degree output of said first 0/180 delay circuit is averaged with said 180 degree output of said second 0/180 delay circuit.

12. The quadrature signal generator of claim 5, wherein said 180-degree output of said first 0/180 delay circuit is averaged with said 0 degree output of said second 0/180 delay circuit.

13. The quadrature signal generator of claim 5, wherein said 90-degree output of a first 90/180 delay circuit is averaged with said 180 degree output of a second 90/180 delay circuit.

14. A quadrature signal generator, comprising:

a coarse stage capable generating quadrature output signals that have substantially a 90 degree phase relationship; and

at least one refinement stage for refining said 90 degree phase relationship of said output signals, said at least one refinement stage including,

a first 0/180 delay circuit having an input that receives a first output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output,

a second 0/180 delay circuit having an input that receives a second output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output,

a third 0/180 delay circuit having an input that receives a third output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output,

a fourth 0/180 delay circuit having an input that receives a fourth output signal of said quadrature output signals, and having a 0 degree output and an 180 degree output,

a first 90/180 delay circuit having an input coupled to said 0 degree output of said first 0/180 delay circuit, and having a 90 degree output and a 180 degree output,

a second 90/180 delay circuit having an input coupled to said 0 degree output of said second 0/180 delay circuit, and having a 90 degree output and a 180 degree output,

a third 90/180 delay circuit having an input coupled to said 0 degree output of said third 0/180 delay circuit, and having a 90 degree output and a 180 degree output,

a fourth 90/180 delay circuit having an input coupled to said 0 degree output of said fourth 0/180 delay circuit, and having a 90 degree output and a 180 degree output,

wherein said 0 degree output of said first 0/180 delay circuit is coupled to said 180 degree output of said third 0/180 delay circuit,

wherein said 180 degree output of said first 0/180 delay circuit is coupled to a 0 degree output of said third 0/180 delay circuit,

wherein said 0 degree output of said second 0/180 delay circuit is coupled to said 180 output of said fourth 0/180 delay circuit,

wherein a 180 degree output of said second 0/180 delay circuit is coupled to a 0 degree output of said fourth 0/180 delay circuit,

wherein said 90 degree output of said first 90/180 delay circuit is coupled to said 180 degree output of said fourth 0/180 delay circuit,

wherein said 180 degree output of said first 90/180 delay circuit is coupled to said 90 degree output of said second 90/180 delay circuit,

wherein a 180 degree output of said second 90/180 delay circuit is coupled to said 90 degree output of said third 0/180 delay circuit, and

wherein a 180 degree output of said third 90/180 delay circuit is coupled to said 90 degree output of said fourth 0/180 delay circuit.

15. A quadrature signal generator, comprising:

a coarse stage capable of generating quadrature output signals that have substantially a 90-degree phase relationship based on a differential input signal; and

at least one refinement stage for refining said quadrature phase relationship of said output signals from said coarse stage, said refinement stage having,

a plurality of 0/180 delay circuits each receiving a corresponding quadrature output signal and having a O-degree output and a 180-degree output, wherein a 0-degree output of a first 0/180 delay circuit is averaged with a 180 degree output of a second 0/180 delay circuit, said first 0/180 delay circuit and said second 0/180 delay circuit separated by a third 0/180 delay circuit,

a plurality of 90/180 delay circuits having inputs coupled to corresponding 0-degree outputs of said plurality of 0/180 delay circuits, wherein a 90-degree output of a first 90/180 delay circuit is averaged with a 180 degree output of a second 90/180 delay circuit, said first 90/180 delay circuit adjacent to said second 90/180 delay circuit.

16. A method of quadrature signal generation, comprising:

receiving a differential input signal;

delaying first and second components of said differential input signal to produce a first set of quadrature signals; and

refining said first set of quadrature signals to reduce phase errors, including

generating second and third sets of quadrature signals based on said first set of quadrature signals, said second set of quadrature signals substantially in-phase with said first set of quadrature signals, said third set of quadrature signals substantially delayed by 180 degrees relative to said first set of quadrature signals,

averaging said second set of quadrature signals with corresponding signals in said third set of quadrature signals, so as to produce a fourth set of quadrature signals,

generating fifth and six sets of quadrature signals based on said fourth set of quadrature signals, said fifth set of quadrature signals delayed by approximately 90 degrees relative to said fourth set of quadrature signals, and said six set of quadrature signals delayed by approximately 180 degrees relative to said first set of quadrature signals,

averaging said fifth set of quadrature signals with corresponding signals in said six set of quadrature signals, so as to produce a seventh set of quadrature signals, whereby said seventh set of quadrature signals has less phase error than said first set of quadrature signals.

17. The method of claim 16, further comprising the step of converting said seventh set of quadrature signals to a set of pulse signals having a quadrature relationship.

18. The method of claim 16, further comprising the step of dividing the frequency of said differential signal by a factor of 2.

19. The method of claim 18, further comprising the step of level shifting said differential signal so as adjust a DC level of said differential signal.

20. The method of claim 16, wherein said step of generating said second and third sets of quadrature signals includes the steps of:

delaying said first set of quadrature signals by approximately 0 degrees to produce said second set of quadrature signals; and

delaying said second set of quadrature signals by approximately 180 degrees to produce said third set of quadrature signals.

21. The method of claim 16, wherein said step of generating said fifth and six sets of quadrature signals includes the steps of:

delaying said fourth set of quadrature signals by approximately 90 degrees to produce said fifth set of quadrature signals; and

delaying said fourth set of quadrature signals by approximately 180 degrees to produce said sixth set of quadrature signals.

22. A quadrature signal generator, comprising:

a differential input having a first and second terminals;

a coarse stage including a first 90/180 delay circuit coupled to said first terminal of said differential input, and a second 90/180 degree delay circuit coupled to said second terminal of said differential input; and

a refinement stage coupled to an output of said coarse stage including,

a plurality of 0/180 delay circuits having inputs coupled to corresponding outputs of said first and second 90/180 delay circuits, each 0/180 delay circuit having a 0 degree output and a 180 degree output, said 0 degree output of each delay circuit connected with said 180 degree output of another 0/180 delay circuit that is substantially in-phase with said 0 degree output, and

a plurality of 90/180 delay circuits having inputs coupled to corresponding outputs of said 0/180 delay circuits, each 90/180 degree delay circuit having a 90 degree output and a 180 degree output, said 90 degree output of each delay circuit connected with said 180 degree output of another 0/180 delay circuit that is substantially in-phase with said 90 degree output.