Simple correlator and integrator for an ultra-wideband (UWB) receiver

• US 20030227984A1
• Filed: 01/02/2003
• Published: 12/11/2003
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Batra, Anuj, Dabak, Anand G., Gharpurey, Ranjit
• Granted Patent: US 7,397,870 B2
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence
• CPC Class Codes: H04B 1/7183 Synchronisation

Abstract

System and method for maximizing a signal strength of a received signal pulse. A preferred embodiment comprises a self-adjusting correlator/integrator (for example, correlator/integrator 325) that uses no historical timing information. The self-adjusting correlator/integrator uses a plurality of simple correlators/integrators (for example, correlator/integrator 805) which are configured to process a received signal at various times surrounding the signal pulse'"'"'s expected arrival. A comparator (for example, comparator 820) selects an output of the simple correlators/integrators with greatest magnitude.

Claims

1. A correlator/integrator comprising:

a signal input;

a first signal path coupled to the signal input, wherein the first signal path is controlled by a first switch, the first signal path to conduct a first signal from the signal input;

a second signal path coupled to the signal input, wherein the second signal path is controlled by a second switch, the second signal path to conduct a second signal from the signal input;

a capacitor coupled to the first and second signal paths, the capacitor to accumulate a charge when either signal is conducted to the capacitor; and

wherein the first signal and the second signals have opposite polarity.

2. The correlator/integrator of claim 1, wherein the first switch is controlled by a first control signal, wherein the second switch is controlled by a second control signal, and the first and second control signals are complements.

3. The correlator/integrator of claim 2, wherein the first and second control signals are specified by an expected shape of a signal from the signal input, wherein the first control signal is active when the signal has a positive polarity, and wherein the first control signal is inactive when the signal has a negative polarity.

4. The correlator/integrator of claim 2, wherein the first and second control signals are periodic.

5. The correlator/integrator of claim 1, wherein the signal is a differential mode signal, wherein the first and second signal paths each comprises two conductors, wherein the first and second switches each comprises two switches, one switch per conductor of each signal path, and wherein the second signal path further comprises a polarity inverter to reverse the signal'"'"'s polarity.

6. The correlator/integrator of claim 5, wherein the two switches of the first switch are controlled by a first control signal, wherein the two switches of the second switch are controlled by a second control signal, and the first and second control signals are complements.

7. The correlator/integrator of claim 1, wherein the signal is a stream of pulses, and wherein any charge on the capacitor is discharged after each pulse.

8. A method for received signal strength maximization comprising:

setting a first correlator/integrator to start operation at a first time, wherein the first correlator/integrator produces an output dependent upon a timing match between the first time and a received signal;

setting a second correlator/integrator to start operation at a second time, wherein the second correlator/integrator produces an output dependent upon a timing match between the second time and the received signal;

setting a third correlator/integrator to start operation at a third time, wherein the third correlator/integrator produces an output dependent upon a timing match between the third time and the received signal;

comparing an output from each of the first, second, and third correlators/integrators; and

selecting a largest output.

9. The method of claim 8, wherein the received signal is a pulse of finite duration, wherein the first time is a time prior to an expected arrival time of the received signal, wherein the second time is a time equal to the expected arrival time of the received signal, and wherein the third time is a time after the expected arrival time of the received signal.

10. The method of claim 9, wherein a difference between the first and second times and the second and third times are equal, and the difference is equal to a specified period of time.

11. The method of claim 10, wherein the difference is approximately equal to one-half of the duration of the received signal.

12. The method of claim 8, wherein the received signal is a pulse of finite duration, wherein the first, second, and third correlators/integrators stop operation after operating for a period of time equal to the duration of the received signal.

13. The method of claim 8, wherein the received signal is a stream of finite duration pulses, and the method repeats for each pulse in the stream.

14. The method of claim 13, wherein the output of each correlator/integrator is reset after each pulse in the stream is received.

15. A self-adjusting pulse detector comprising:

a signal input to provide a signal;

a plurality of correlators/integrators coupled to the signal input, each correlator/integrator containing circuitry to correlate a signal from the signal input with a desired signal and to create a value based on the correlation, wherein each correlator/integrator is configured to commence operation at a different time; and

a comparator having a plurality of inputs, with each input coupled to an output from each of the plurality of correlators/integrators, the comparator to select a maximum output from the plurality of inputs.

16. The self-adjusting pulse detector of claim 15, wherein the signal input provides a stream of finite duration pulses, wherein each finite duration pulse has an expected arrive time, wherein there are three correlators/integrators, wherein a first correlator/integrator commences operation prior to the expected arrival time of each finite duration pulse, wherein a second correlator/integrator commences operation at the expected arrival time of each finite duration pulse, and wherein a third correlator/integrator commences operation after the expected arrival time of each finite duration pulse.

17. The self-adjusting pulse detector of claim 16, wherein a first time difference between a starting time of the first and second correlators/integrators is equal to a second time difference between a starting of the second and third correlators/integrators, and wherein the first and second time differences are equal.

18. The self-adjusting pulse detector of claim 15, wherein each correlator/integrator comprises:

a first signal path coupled to the signal input, wherein the first signal path is controlled by a first switch, the first signal path to conduct a first signal from the signal input;

a second signal path coupled to the signal input, wherein the second signal path is controlled by a second switch, the second signal path to conduct a second signal from the signal input;

a capacitor coupled to the first and second signal path, the capacitor to accumulate a charge when either signal is conducted to the capacitor;

wherein when the first switch and the second switch operate in opposing fashion; and

wherein the first signal and the second signals have opposite polarity.

19. The self-adjusting pulse detector of claim 18, wherein the signal is a stream of pulses, and wherein the capacitor in each correlator/integrator is reset after each pulse.

20. An ultra-wideband (UWB) receiver comprising:

a signal input;

a filter and amplifier unit (FAU) coupled to the signal input, the FAU containing circuitry to eliminate interferers and amplify a signal provided by the signal input to an specified magnitude;

a self-adjusting pulse detector coupled to the FAU, the self-adjusting correlator/integrator containing circuitry to maximize a signal strength of an output provided by the FAU; and

a baseband processor coupled to the self-adjusting correlator/integrator, the baseband processor containing circuitry to equalize and decode a data stream provided by the self-adjusting correlator/integrator.

21. The UWB receiver of claim 20, wherein the signal is a stream of finite duration pulses.

22. The UWB receiver of claim 20, wherein the self-adjusting pulse detector comprises:

a plurality of correlators/integrators coupled to the signal input, each correlator/integrator containing circuitry to correlate a signal from the signal input with a desired signal and to create a value based on the correlation, wherein each correlator/integrator is configured to commence operation at a different time; and

a comparator having a plurality of inputs, with each input coupled to an output from each of the plurality of correlators/integrators, the comparator to select a maximum output from the plurality of inputs.

23. The UWB receiver of claim 22, wherein there are three correlators/integrators in the self-adjusting pulse detector.

24. The UWB receiver of claim 22, wherein the signal is a stream of finite duration pulses, and wherein each correlator/integrator comprises a capacitor that is reset after each finite duration pulse.