Method and apparatus for clock-and-data recovery using a secondary delay-locked loop

• US 20030227989A1
• Filed: 06/07/2002
• Published: 12/11/2003
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Friedman, Daniel, Soyuer, Mehmet, Gowda, Sudhir, Rhee, Woogeun
• Granted Patent: US 7,197,102 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A clock and data recovery circuit includes a delay-locked-loop adapted to recover data from a data stream: and a phase-locked-loop in communication with the delay-locked-loop and adapted to recover a clock signal from the data stream.

Claims

1. A clock and data recovery circuit comprising:

a delay-locked-loop adapted to recover data from a data stream; and

a phase-locked-loop in communication with said delay-locked-loop and adapted to recover a clock signal from said data stream.

2. The circuit of claim 1, wherein the phase-locked-loop is also adapted to track long term jitter.

3. The circuit of claim 1, wherein the delay-locked-loop is also adapted to track short term jitter.

4. The circuit of claim 1, wherein said delay-locked-loop has a wider bandwidth than said phase-locked-loop.

5. The circuit of claim 1, wherein said delay-locked-loop comprises a self-calibrating voltage-controlled delay line.

6. The circuit of claim 5, wherein said voltage-controlled delay line receives the data stream.

7. The circuit of claim 5, wherein said voltage-controlled delay line receives a recovered clock signal from said phase-locked-loop.

8. The circuit of claim 1, further comprising a D-type flip flop in communication with said delay-locked-loop.

9. The circuit of claim 1, further comprising a 1/nth-rate demultiplexer.

10. The circuit of claim 9, wherein the 1/nth-rate demultiplexer comprises a half-rate demultiplexer.

11. The circuit of claim 9, wherein the 1/nth-rate demultiplexer comprises a quarter-rate demultiplexer.

12. The circuit of claim 1, wherein said delay-locked-loop comprises a phase detector.

13. The circuit of claim 2, wherein said phase detector comprise a binary phase detector.

14. The circuit of claim 2, wherein said phase detector comprises a half-rate phase detector.

15. The circuit of claim 1, wherein said delay-locked-loop comprises a charge pump.

16. The circuit of claim 1, wherein said delay-locked-loop comprises a divider.

17. The circuit of claim 1, further comprising another delay-locked-loop in communication with said phase-locked-loop.

18. A method of recovering clock and data signals from a data stream, comprising:

recovering data from said data stream in a delay-locked-loop;

receiving said data stream in a phase-locked-loop from said delay-locked loop; and

recovering a clock signal from said data stream in said phase-locked-loop.

19. A circuit for recovering clock and data signals from a data stream, comprising:

means for extracting a clock signal from said data stream; and

means for extracting data from said data stream, wherein said means for extracting said clock signal and said means for extracting data are independent to optimally allocate bandwidth.

20. A circuit for recovering clock and data signals from a data stream, comprising:

means for recovering data from said data stream in a delay-locked-loop;

means for receiving said data stream in a phase-locked-loop from said delay-locked loop; and

means for recovering a clock signal from said data stream in said phase-locked-loop.