Dummy fill for integrated circuits

• US 20030228714A1
• Filed: 06/07/2002
• Published: 12/11/2003
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: White, David, Smith, Taber H., Mehrotra, Vikas
• Granted Patent: US 7,393,755 B2
• Time in Patent Office: Days
• US Class Current: 438/8
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Claims

1. A method comprising

based on electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, generating a strategy for placement of dummy fill in the process, and

using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the dummy fill to be placed,

the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill placement strategy.

5. The method of claim 1, 2, or 3 also including operating a server to provide dummy fill generation functions for a semiconductor design, and

enabling a user at a client to operate through a web browser to develop the dummy fill placement strategy.

6. The method of claim 5 in which the server is local to the user.

7. The method of claim 6 in which the server is remote from the user.

8. The method of claim 1, 2, or 3 also including

analyzing a design to which the dummy fill strategy has been applied,

adjusting the design based on the analysis,

iterating the analyzing and adjusting steps, and

certifying that an integrated circuit manufactured according to the adjusted design will be within predefined physical and electrical parameters.

13. The method of claim 1, 2, 3 or 4 also including

defining a set of hierarchical cell placements for dummy fill, and

reducing a size of an electronic layout file to which dummy fill is added by using the hierarchical cell placements.

14. The method of claim 1, 2, 3 or 4 in which the dummy fill generation is performed by a user through a web browser and a web server.

15. The method of claim 14 in which the web server is local to the user.

16. The method of claim 14 in which the web server is remote from the user.

17. The method of claims 1, 2, 3 or 4 in which the process comprises a damascene process.

18. The method of claim 1, 2, 3 or 4in which the strategy for placement of dummy fill includes determining the size and placement of dummy fill.

19. The method of claim 1, 2, 3 or 4 in which the fabrication process comprises a formation of a low-K interlayer dielectric.

21. The method of claim 1, 2, 3 or 4 in which generating the dummy fill strategy includes dividing a semiconductor design into grids.

22. The method of claim 21 in which generating the dummy fill strategy also includes extracting local pattern densities for a semiconductor design for each of the grids.

23. The method of claim 21 in which generating the dummy fill strategy also includes extracting local line width for a semiconductor design for each of the grids.

24. The method of claim 21 in which generating the dummy fill strategy also includes extracting local line spacing for a semiconductor design for each of the grids.

25. The method of claim 21 in which generating the dummy fill strategy also includes computing an effective pattern density for each grid.

26. The method of claim 22, also including using models for computing film thickness non-uniformity with respect to a semiconductor design for which the dummy fill strategy is being generated.

27. The method of claim 26 also including computing a variation in film thickness.

28. The method of claim 21 also including deriving coordinates of all objects within each of the grids.

29. The method of claim 28 also including generating at least one of line width, line space, length, and bounding box with respect to each of the objects.

30. The method of claim 21 in which the dummy fill strategy includes adding dummy fill in empty areas of each of the grids.

31. The method of claim 28 in which the dummy fill includes slots in objects.

32. The method of claim 30 comprising re-computing a local density in each of the grids after adding dummy fill.

33. The method of claim 30 also comprising re-computing an effective pattern density for each of the grids after adding dummy fill.

34. The method of claim 1, 2, 3 or 4 in which the dummy fill strategy is based on criteria for electrical parameter variation tolerances for at least one of the following:

capacitance and resistance, sheet resistance, outputs delay, skew, voltage drop, drive current loss, dielectric constant or crosstalk noise.

35. The method of claim 33 in which the effective pattern density is computed based on a polishing process planarization length.

36. The method of claim 33 in which the effective pattern density is computed using an elliptically weighted window or other filter.

38. The method of claim 35 in which an effective pattern density is generated dynamically with a change in a process planarization length.

39. The method of claim 1, 2, 3 or 4 in which the fabrication process comprises lithography.

40. The method of claim 1, 2, 3 or 4 in which the fabrication process comprises electrochemical deposition.

41. The method of claim 1, 2, 3 or 4 in which the fabrication process comprises copper chemical mechanical polishing.

42. The method of claims 1, 2, 3 or 4 also including extracting pattern dependencies from a layout of the semiconductor.

43. The method of claim 42 in which the layout dependencies include with respect to line spacing, line width or line density.

44. The method of claim 1, 2, 3 or 4 also including

using patterned test wafers or test semiconductor devices to calibrate a pattern dependent model with respect to a preselected tool or process recipe, and

based on a pattern dependent model of a semiconductor fabrication process, generating the strategy for placement of dummy fill in the process.

45. The method of claim 1, 2, 3 or 4 also comprising

using a calibrated pattern dependent model to map pattern dependent features to wafer-state parameters such as resulting film thickness, film thickness variation, dishing, erosion and electrical parameters such as sheet resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, dielectric constant and effective dielectric constant, and

based on the pattern dependent model, generating the strategy for placement of dummy fill in a fabrication process.

46. The method of claim 1, 2, 3 or 4 also comprising

based on a pattern dependent model, generating a strategy for placement of dummy fill in a process, and

using a cost function to measure an impact of dummy fill modification on process induced wafer state and electrical parameter variation.

47. The method of claim 1, 2, 3 or 4 also comprising

based on a combination of more than one pattern dependent model, generating a strategy for placement of dummy fill in a process, and

predicting an impact of the dummy fill generated by the strategy on process variation.

48. The method of claim 1, 2, 3 or 4 also comprising

based on a combination of more than one pattern dependent model and cost function, generating a strategy for placement of dummy fill in a process that optimizes full-chip wafer-state and electrical parameters

49. The method of claim 1, 2, 3 or 4 also comprising

based on predicted or simulated wafer state and electrical parameters, generating dummy fill rules for use in dummy fill placement in a semiconductor fabrication process.

50. The method of claim 49 in which the dummy fill rules include dummy fill sizing.

51. The method of claim 49 in which the dummy fill rules include dummy fill placement.

52. The method of claim 49 in which the dummy fill rules include dummy fill hierarchical cell creation and management.

53. The method of claim 1, 2, 3 or 4 also comprising

providing dummy fill functions to generate the dummy fill strategy, and

using the functions to automatically modify GDS-format electronic layout files for a semiconductor device.

54. The method of claim 1, 2, 3 or 4 also comprising

at an internet server, receiving from a client a layout file for a semiconductor device,

generating dummy fill modifications to the layout file at the server, and

returning the dummy fill modified layout file from the server to the client.

55. The method of claim 1, 2, 3 or 4 also comprising

at a server, providing a service that enables a user to interactively configure a dummy fill application running on the server, and

enabling the user to generate dummy fill information using the dummy fill application.

56. The method of claim 1, 2, 3 or 4 also comprising

making available to a user on a network a service that enables the user to verify dummy fill information with respect to a semiconductor design and a fabrication process.

57. The method of claim 56 in which the dummy fill information that is verified includes at least one of a dummy fill pattern, a dummy fill strategy, or a dummy fill representation.

58. The method of claim 56 in which the dummy fill information is verified with respect to a single interconnect level of the semiconductor design.

59. The method of claim 56 in which the dummy fill information is verified with respect to multiple interconnect levels of the semiconductor design.

60. The method of claim 56 also including sizing dummy fill objects and creating a dummy fill pattern of the objects for one or more interconnect levels of the semiconductor design.

61. The method of claim 56 in which the dummy fill information comprises dummy fill rules.

62. The method of claim 60 in which the pattern includes oxide or metal dummy fill objects.

63. The method of claim 60 in which the objects of the dummy fill pattern are placed to minimize full-chip film thickness variation.

64. The method of claim 60 in which the objects of the dummy fill pattern are placed to minimize full-chip variation in electrical parameters.

65. The method of claim 64 in which the electrical parameters comprise at least one of sheet resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, and effective dielectric constant.

66. The method of claim 53 in which the GDS files are modified to improve uniformity and electrical performance of the semiconductor device.

67. The method of claim 66 in which the process comprises a damascene process flow.

68. The method of claim 1, 2, 3 or 4 also comprising

making available to a user on a network a web-based application comprised of web services that enables the user to verify dummy fill information with respect to a semiconductor design and a fabrication process.

69. The method of claim 1, 2, 3 or 4 in which the dummy fill placement strategy includes using dummy fill objects to improve a structural integrity of low-K dielectric features.

70. The method of claim 1, 2, 3 or 4 in which the dummy fill placement strategy includes using dummy fill objects to maintain or improve an effective dielectric constant of low-K dielectric features.

71. The method of claim 60 or 70 in which the effective dielectric constant is maintained through all steps of a damascene process flow.

72. The method of claim 1, 2, 3 or 4 in which the dummy fill placement strategy includes using dummy fill objects to facilitate integration of low-k dielectric materials into a damascene process flow.

73. The method of claim 1, 2, 3 or 4 also comprising

maintaining a library of semiconductor dummy fill information, and

making the library available for use in connection with generating dummy fill placement specifications, and

updating the library with changed dummy fill information.

74. The method of claim 1, 2, 3 or 4 also comprising

storing calibration information with respect to at least one of the following:

process tools, recipes, and flows, and

updating the calibration information to reflect changes in the process tools, recipes or flows.

75. The method of claim 74 also including using the calibration information in generating a dummy fill strategy.

76. The method of claim 74 also including selecting among process tools, recipes and flows from calibration database based upon desired dummy fill characteristics.

77. The method of claim 1, 2, 3 or 4 also comprising

enabling a user to obtain a dummy fill strategy for a semiconductor design using a single click of a user interface device through a user interface.

78. The method of claim 1, 2, 3 or 4 also comprising

enabling a user to obtain a dummy fill strategy for a semiconductor design over the internet using web services.

2. A method comprising

based on an electrical impact analysis and a pattern dependent model of a chemical mechanical polishing process, generating a strategy for placement of dummy fill in the process, and

using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the dummy fill to be placed,

the fabrication process for which the strategy is being generated comprising other than an oxide chemical mechanical polishing process.

3. A method comprising

based on a pattern dependent model of a chemical mechanical polishing process, generating a strategy for placement of dummy fill in the process, and

using the pattern dependent model to evaluate the expected results of the dummy fill to be placed,

the fabrication process for which the strategy is being generated comprising two or more stages of fabrication.

9. The method of claim 3 in which the two stages comprise two or more processes.

10. The method of claim 3 in which the two stages comprise two or more steps of a single process.

11. The method of claim 3 in which the two stages comprise deposition and chemical mechanical polishing.

12. The method of claim 3 in which the generating of a strategy includes generating dummy fill rules.

20. The method of claim 3 in which the fabrication process comprises chemical vapor deposition or spin-on of the low-K dielectric.

37. The method of claim 12 in which dummy fill rules based on electrical design guidelines are generated dynamically with a change in technology or design parameters.

4. A method comprising

based on a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process, and

using the pattern dependent model to evaluate the expected results of the dummy fill to be placed,

the fabrication process for which the strategy is being generated comprising a polishing or planarization process in which more than one material is removed.