Integrated circuit metrology
First Claim
1. A method comprising selecting sites to be measured on a device that is to be fabricated using at least one fabrication process, the sites being selected based on a pattern-dependent model of the process.
2 Assignments
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Accused Products
Abstract
Sites to be measured on a device that is to be fabricated using at least one fabrication process, are selected based on a pattern-dependent model of the process. A metrology tool to measure a parameter of a semiconductor device includes a control element to select sites for measurement based on a pattern dependent model of a process with respect to the device. Problematic areas, within a chip or die and within a wafer, are identified that result from process variation. The variation is identified and characterized, and the location of each site is stored. The sites may be manually entered into a metrology tool or the method will automatically generate a measurement plan. Process variation and electrical impact are used to direct the measurement of within-die and wafer-level integrated circuit locations.
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Citations
105 Claims
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1. A method comprising
selecting sites to be measured on a device that is to be fabricated using at least one fabrication process, the sites being selected based on a pattern-dependent model of the process.
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2. A method comprising
selecting sites to be measured on a device that is to be fabricated using at least one fabrication process, the sites being selected based on an electrical impact analysis of the process.
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51. A method comprising selecting measurement sites for an entire semiconductor chip, the sites being selected based upon a pattern-dependent model for a single interconnect level of the chip.
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52. A method comprising
selecting measurement sites for an entire semiconductor chip, the sites being selected based upon a pattern-dependent model for multiple interconnect levels of the chip.
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53. A method comprising
measuring a device under fabrication in accordance with a measurement plan that is based on a pattern-dependent model of the fabrication, and verifying predicted variations in wafer-state parameters during fabrication.
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55. A method comprising
measuring a device that has been subjected to a chemical mechanical polishing process in accordance with a measurement plan that is based on a pattern-dependent model, and identifying areas of the device in which the chemical mechanical polishing process resulted in incomplete removal of material.
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56. A method comprising
measuring a semiconductor device in accordance with a measurement plan that is based on a pattern-dependent model in order to identify characteristics of residual copper remaining on the device after processing, and using results of the measurement as feedback to a process control system.
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57. A method comprising
measuring a semiconductor device in accordance with a measurement plan that is based on a pattern-dependent model in order to identify characteristics of residual copper remaining on the device after processing, and using results of the measurement as feedback to a process for recipe synthesis.
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64. A method comprising
using test structures and reference materials and pattern-dependent models to correlate scribe line measurement and on-chip properties.
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75. A method comprising
selecting sites to be measured on a semiconductor device that is being fabricated, measuring the sites, rejecting the device if the result of the measuring of the site indicates that the device does not meet a requirement, selecting other sites to be measured on the semiconductor device, measuring the other sites, and rejecting the device if the result of the measuring of the other sites indicates that the device does not meet a requirement.
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86. A method comprising
selecting sites to be measured on a device that is to be fabricated using at least one fabrication process, the process including clearing of material from a surface of the device, the sites being selected based on a pattern-dependent model of the process to test whether clearing has occurred within an acceptable tolerance.
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99. A method comprising
measuring a semiconductor device in accordance with a measurement plan that is based on a plasma etch pattern-dependent model in order to identify critical dimensions of IC features.
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105. Apparatus comprising
a metrology tool to measure a parameter of a semiconductor device, the metrology tool including a control element to select sites for measurement based on a pattern dependent model of a process with respect to the device.
Specification