Integrated circuit metrology

• US 20030229410A1
• Filed: 07/22/2002
• Published: 12/11/2003
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: White, David, Smith, Taber H.
• Granted Patent: US 7,363,099 B2
• Time in Patent Office: Days
• US Class Current: 700/109
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]

Abstract

Sites to be measured on a device that is to be fabricated using at least one fabrication process, are selected based on a pattern-dependent model of the process. A metrology tool to measure a parameter of a semiconductor device includes a control element to select sites for measurement based on a pattern dependent model of a process with respect to the device. Problematic areas, within a chip or die and within a wafer, are identified that result from process variation. The variation is identified and characterized, and the location of each site is stored. The sites may be manually entered into a metrology tool or the method will automatically generate a measurement plan. Process variation and electrical impact are used to direct the measurement of within-die and wafer-level integrated circuit locations.

Claims

1. A method comprising

selecting sites to be measured on a device that is to be fabricated using at least one fabrication process,

the sites being selected based on a pattern-dependent model of the process.

3. The method of claim 1 also including selecting the sites based on an electrical impact analysis of the process.

4. The method of claim 1 in which the process comprises chemical mechanical polishing.

5. The method of claim 1 in which the selecting of sitesis based on a measurement strategy.

6. The method of claim 1 in which the selected sites are part of a measurement recipe.

7. The method of claim 1 in which the selected sites correspond to a measurement strategy.

8. The method of claim 1 in which the process comprises electrical chemical deposition.

9. The method of claim 1 in which the process comprises two or more stages.

10. The method of claim 9 in which the two stages comprise two or more processes.

11. The method of claim 9 in which the two stages comprise two or more steps of a single process.

12. The method of claim 9 in which the two stages comprise deposition and chemical mechanical polishing.

13. The method of claim 9 in which the selected sites include within-die and within-wafer (die-to-die) measurement sites.

14. The method of claim 9 in which one of the two stages comprises lithography.

15. The method of claim 9 in which one of the two stages comprises plasma etch.

16. The method of claim 1 also including

using patterned test wafers or test semiconductor devices to calibrate the pattern dependent model with respect to a preselected tool or process recipe.

17. The method of claim 1 in which the pattern dependent model maps pattern dependent features to wafer-state parameters that include at least one of:

resulting film thickness, film thickness variation, dishing, or erosion.

18. The method of claim 1 in which the pattern dependent model maps pattern dependent features to electrical parameters that include at least one of sheet resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, dielectric constant, and effective dielectric constant.

19. The method of claim 1 or 2 also comprising

using a cost function to determine which sites to measure.

20. The method of claim 1 or 2 in which the selection of sites is based on more than one pattern dependent model.

21. The method of claim 19 also comprising

using the cost function to select sites to measure the impact of dummy fill.

22. The method of claim 1 or 2 also comprising

at an internet server, receiving from a client a layout file and design specifications for the device,

selecting the sites at the server, and

returning information identifying the selected sites from the server to the client.

23. The method of claim 1 or 2 also comprising making available to a user on a network a service that enables the user to cause the selection of sites with respect to a semiconductor design, a fabrication process, and metrology device.

24. The method of claim 1 in which the sites are selected with respect to a single interconnect level of the device.

25. The method of claim 1 in which the measurement plan is generated with respect to multiple interconnect levels of the device.

26. The method of claim 1 in which the device comprises at least one of a semiconductor wafer or a semiconductor chip within a wafer.

27. The method of claim 1 or 2 in which the selecting of sites includes using dummy fill objects to improve a structural integrity of low-K dielectric features.

28. The method of claim 1 or 2 in which the selecting of sites includes using dummy fill objects to maintain or improve an effective dielectric constant of low-K dielectric features.

29. The method of claim 27 in which the effective dielectric constant is maintained through all steps of a damascene process flow.

30. The method of claim 28 in which the effective dielectric constant is maintained through all steps of a damascene process flow.

31. The method of claim 1 or 2 in which the selecting of sites includes using dummy fill objects to facilitate integration of low-k dielectric materials into a damascene process flow.

32. The method of claim 1 or 2 also comprising

maintaining a library of sites,

making the library available for use in connection with generating measurement strategies, and

updating the library with respect to of new or improved metrology tools..

33. The method of claim 1 or 2 also comprising

storing calibration information with respect to at least one of the following:

process tools, recipes, and flows, and

updating the calibration information to reflect changes in the process tools, recipes or flows.

34. The method of claim 1 or 2 also comprising

enabling a user to selection of sites for a device using a single click of a user interface device through a user interface.

35. The method of claim 1 or 2 also comprising

enabling a user to obtain selection of sites for a device over the internet using web services.

36. The method of claim 1 or 2 also comprising

making available to a user on a network a service that enables the user to verify sites with respect to the device and a fabrication process or flow.

37. The method of claim 1 or 2 in which the sites are seelcted to characterize variation in electrical parameters.

38. The method of claim 37 in which the electrical parameters comprise at least one of sheet resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, and effective dielectric constant.

39. The method of claims 1 or 2 also including

extracting pattern dependencies from a layout of the device.

40. The method of claim 39 in which the pattern dependencies include dependencies with respect to line spacing, line width or line density.

41. The method of claim 1 or 2 also including using the selected sites to provide feedback to a process control system or a recipe synthesis tool.

42. The method of claim 1 or 2 in which the sites are selected for a semiconductor die.

43. The method of claim 1 or 2 in which the sites are selected for one or more die within a wafer.

44. The method of claim 1 or 2 in which the sites are selected for one or more wafers within a lot.

45. The method of claim 1 or 2 in which the sites are selected for one or more lots within a production run.

46. The method of claim 1 or 2 in which the sites are selected within a metrology tool.

47. The method of claim 1 or 2 in which the sites are selected within a process control or advanced process control system.

48. The method of claim 1 or 2 in which the selected sites are electronically or optically communicated to a process or metrology tool across an extranet network, intranet network, internet network or a virtual private network.

49. The method of claim 1 or 2 in which the sites are selected based on criteria for electrical parameter variation tolerances for at least one of the following:

capacitance and resistance, sheet resistance, outputs delay, skew, voltage drop, drive current loss, dielectric constant or crosstalk noise.

50. The method of claim 1 or 2 in which the sites are selected based on criteria for wafer parameter variation tolerances for at least one of the following:

film thickness, dishing and erosion.

58. The method of claim 1 in which the sites are selected as part of an automatic generation of a measurement plan, a measurement recipe, or a sample plan for metrology equipment.

59. The method of claim 58 in which the metrology equipment comprises optical metrology equipment

60. The method of claim 58 in which the metrology equipment comprises profilometry metrology equipment

61. The method of claim 58 in which the metrology equipment comprises electrical probe metrology equipment.

62. The method of claim 58 in which the metrology equipment comprises in-situ or in-line metrology equipment within cluster tools or stations.

63. The method of claim 62 also including

enabling feedback process control within the cluster tools or stations

65. The method of claim 1 in which the sites are to be measured in at least one of in-line metrology, in-situ metrology, or off-line metrology.

66. The method of claim 1 in which the process comprises part of a damascene process flow.

67. The method of claim 1 in which the process comprises introduction of low-k materials into a damascene process flow.

68. The method of claim 1 in which the process comprises introduction of low-k ILD materials into a damascene process flow.

69. The method of claim 1 in which the process includes use of dummy fill to improve structural properties of low-k ILD.

71. The method of claim 1 in which the sites are selected to characterize pattern dependencies in a plasma etch process or tool.

72. The method of claim 1 in which the sites are selected to characterize IC pattern dependencies in a lithography process or tool.

73. The method of claim 1 in which the sites are selected to characterize IC pattern dependencies in a chemical mechanical polishing process or tool.

74. The method of claim 1 in which the sites are selected to characterize IC pattern dependencies in the formation of interconnect structures.

84. The method of claim 1 in which the sites are selected at a die level.

85. The method of claim 1 in which the sites are selected at a wafer level.

88. The method of claim 1 also including controlling a metrology tool in response to the selecting.

89. The method of claim 88 in which the metrology tool comprises a optical reflectance, CD, profilometry, acoustic or eddy current metrology tool.

90. The method of claim 1 also including characterizing full-chip or wafer-level parametric yield using the measurements.

91. The method of claim 1 in which the sites are selected based oil minimum or maximum features that may violate design specifications of the device.

97. The method of claim 1 also including

enabling the comparison and selection among best-known process methods and consumables.

98. The method of claim 1 also including

enabling feedback to adapt settings or recipe parameters for a plasma etch process tool or a flow including a plasma etch tool.

100. The method of claim 1 in which the pattern dependent model maps pattern dependent features to wafer-state parameters that include at least one of resulting critical dimension (CD), film thickness, aspect ratio or trench width or trench depth.

101. The method of claim 1 also including

enabling feedback to adapt settings or recipe parameters for a lithography tool or a flow including a lithography tool.

102. The method of claim 1 also including

enabling the adjustment of design rules, design specifications or control bands.

103. The method of claim 1 also including

enabling the design of test structures or devices.

104. The method of claim 1 also including

enabling the correlation of chip parameters with existing test structures or devices.

2. A method comprising

selecting sites to be measured on a device that is to be fabricated using at least one fabrication process,

the sites being selected based on an electrical impact analysis of the process.

70. The method of claim 2 in which the electrical impact analysis comprises assessment of effective dielectric constant.

51. A method comprising selecting measurement sites for an entire semiconductor chip, the sites being selected based upon a pattern-dependent model for a single interconnect level of the chip.

52. A method comprising

selecting measurement sites for an entire semiconductor chip, the sites being selected based upon a pattern-dependent model for multiple interconnect levels of the chip.

53. A method comprising

measuring a device under fabrication in accordance with a measurement plan that is based on a pattern-dependent model of the fabrication, and

verifying predicted variations in wafer-state parameters during fabrication.

54. The method of claim 53 also including verifying predicted variations in electrical parameters during fabrication.

55. A method comprising

measuring a device that has been subjected to a chemical mechanical polishing process in accordance with a measurement plan that is based on a pattern-dependent model, and

identifying areas of the device in which the chemical mechanical polishing process resulted in incomplete removal of material.

56. A method comprising

measuring a semiconductor device in accordance with a measurement plan that is based on a pattern-dependent model in order to identify characteristics of residual copper remaining on the device after processing, and

using results of the measurement as feedback to a process control system.

57. A method comprising

measuring a semiconductor device in accordance with a measurement plan that is based on a pattern-dependent model in order to identify characteristics of residual copper remaining on the device after processing, and

using results of the measurement as feedback to a process for recipe synthesis.

64. A method comprising

using test structures and reference materials and pattern-dependent models to correlate scribe line measurement and on-chip properties.

75. A method comprising

selecting sites to be measured on a semiconductor device that is being fabricated, measuring the sites,

rejecting the device if the result of the measuring of the site indicates that the device does not meet a requirement,

selecting other sites to be measured on the semiconductor device,

measuring the other sites, and

rejecting the device if the result of the measuring of the other sites indicates that the device does not meet a requirement.

76. The method of claim 75 also including

repeating the selecting, measuring, and rejecting the steps.

77. The method of claim 75 in which the measuring is performed in-line with respect to a processing step.

78. The method of claim 75 in which the measuring is performed in-situ with respect to a processing step.

79. The method of claim 75 in which the measuring is performed off-line with respect to a processing step.

80. The method of claim 75 in which the selecting is done by software included within a metrology tool.

81. The method of claim 75 in which the selecting is based on a pattern-dependent model of the process with respect to the device.

82. The method of claim 81 in which the model is calibrated with respect to a particular tool for the process.

83. The method of claim 81 in which the model incorporates variation of the process over time, and the selecting is based on the model configured for a time associated with the time when the measurement is to be taken.

86. A method comprising

selecting sites to be measured on a device that is to be fabricated using at least one fabrication process, the process including clearing of material from a surface of the device,

the sites being selected based on a pattern-dependent model of the process to test whether clearing has occurred within an acceptable tolerance.

87. The method of claim 86 in which the process includes polishing and the acceptable tolerance includes clearance without overpolishing.

92. The method of claim 86 also including

enabling feedback to adapt settings or recipe parameters in a chemical mechanical polishing tool.

93. The method of claim 86 also including

enabling feedback to adapt settings or recipe parameters in an electrical chemical mechanical deposition tool or a flow including an electrical chemical mechanical deposition tool.

94. The method of claim 86 also including

enabling feedback to adapt differential pressures in a chemical mechanical polishing tool head.

95. The method of claim 86 also including

enabling feedback to adapt recipe parameters in a process step.

96. The method of claim 86 also including

enabling feedback to synthesize recipe parameters in a process flow.

99. A method comprising

measuring a semiconductor device in accordance with a measurement plan that is based on a plasma etch pattern-dependent model in order to identify critical dimensions of IC features.

105. Apparatus comprising

a metrology tool to measure a parameter of a semiconductor device, the metrology tool including a control element to select sites for measurement based on a pattern dependent model of a process with respect to the device.