Emulation system for data-driven processor

• US 20030229485A1
• Filed: 01/24/2003
• Published: 12/11/2003
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Semiconductor Technology Academic Research Center
• Original Assignee: Semiconductor Technology Academic Research Center
• Inventors: Wabiko, Yasuhiro, Ito, Shinya, Kurebayashi, Ryosuke, Nishikawa, Hiroaki
• Granted Patent: US 6,813,703 B2
• Time in Patent Office: Days
• US Class Current: 703/25
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

Abstract

An emulation system for data-driven processors which aims at shortening the emulation time by employing parallel processing techniques without increasing overhead. The emulation system emulates virtual data-driven processors by using real data-driven processors. The emulation is performed by dividing the functionality of the processor into a data path and a timing path. In the data path emulation, each virtual packet to be processed in the virtual processor is expressed as a PACKET message, and the processing operation of the virtual packet is evaluated for each functional block. In the timing path emulation, a SEND signal and an ACK signal, to be controlled by a self-timed transfer control mechanism and a gate logic, are expressed as a SEND message and an ACK message, respectively, and stage-to-stage transfer operations of the SEND signal and the ACK signal are evaluated.

Claims

1. A data-driven processor emulation system which, using real data-driven processors, emulates virtual data-driven processors each organized as a pipeline consisting of a sequence of stages, each stage having a data latch for holding a packet, a logic circuit for processing the packet held in said data latch, a self-timed transfer control mechanism for supplying a synchronizing signal to said data latch, and an optional gate logic for controlling, based on processing results from said logic circuit, a SEND signal and an ACK signal transferred between said self-timed transfer control mechanism in said stage and a self-timed transfer control mechanism in a downstream stage, wherein each of said real data-driven processors comprises:

data path emulation means for expressing a virtual packet, to be processed in said virtual data-driven processors, as a PACKET message which is a packet to be processed in said real data-driven processor, and for evaluating processing operation of said virtual packet for each functional block within said virtual data-driven processors; and

timing path emulation means for expressing said SEND signal and said ACK signal, to be controlled by said self-timed transfer control mechanism and said gate logic, as a SEND message and an ACK message, respectively, which are packets to be processed in said real data-driven processor, and for evaluating stage-to-stage transfer operations of said SEND signal and said ACK signal.

2. A data-driven processor emulation system as claimed in claim 1, wherein said timing path emulation means evaluates the position of said virtual packet at a given time by appending a timestamp to each of said SEND message and said ACK message.

3. A data-driven processor emulation system as claimed in claim 1, wherein said timing path emulation means evaluates control operation of said SEND signal and said ACK signal at said gate logic by receiving a CONTROL message representing the result of the evaluation from said data path emulation means.

4. A data-driven processor emulation system as claimed in claim 1, wherein said data path emulation means processes a plurality of PACKET messages in parallel by assigning a unique identifier to each virtual packet.

5. A data-driven processor emulation system as claimed in claim 1, wherein said timing path emulation means processes said SEND message and said ACK message in parallel by assigning a unique identifier on a stage-by-stage basis.

6. A data-driven processor emulation system as claimed in claim 1, further comprising a von Neumann computer which is connected to said real data-driven processor via a computer network, and which performs processing for generating emulation information and displaying the result of the emulation.

7. A data-driven processor emulation system as claimed in claim-6, wherein said von Neumann computer creates in advance packet flow information in which information concerning each individual virtual packet is described, and said data path emulation means determines the behavior of said virtual packet by referring to said packet flow information.

8. A data-driven processor emulation system as claimed in claim 6, wherein said von Neumann computer receives, from said real data-driven processor, trace information concerning the position and time of each virtual packet, and displays a pipeline occupancy graph plotting the ratio of the number of stages where packets are present to the total number of stages as a function of time.