Memory protection system and method for computer architecture for broadband networks

• US 20030229765A1
• Filed: 02/21/2003
• Published: 12/11/2003
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Yamazaki, Takeshi, Suzuoki, Masakazu
• Granted Patent: US 7,139,882 B2
• Time in Patent Office: Days
• US Class Current: 711/150
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

Claims

1. A computer processing system, said processing system comprising:

a first memory for storing programs and data associated with said programs;

a plurality of first processing units for processing said programs and said associated data;

a memory controller for controlling accesses to said first memory by said first processing units;

a second memory for storing an access table and a key table, said access table comprising a plurality of access entries, each said access entry including an access key and an identification of a memory space within said first memory associated with said access key, said key table comprising a plurality of key entries, each said key entry including an identification of one of said first processing units and a request key associated with said first processing unit;

a second processing unit for controlling said processing of said programs and said associated data by said first processing units, said second processing unit being operable to construct and maintain said access table and said key table, said second processing unit being further operable to direct any one of said first processing units to process one of said programs, said one first processing unit being operable in processing said one program to issue a request to said memory controller for access to a storage location within said first memory, said memory controller being operable, in response to said request, to compare the request key associated with said one processing unit in said key table with the access keys in said access table, and if one of said access keys corresponds with the request key associated with said one first processing unit in said key table and said storage location corresponds to the memory space associated with said one access key identified in said access table, to execute said request.

2. A computer processing system as in claim 1, further comprising a plurality of local memories, each of said local memories being associated with one of said first processing units, and wherein said second processing unit is operable to direct said one first processing unit to process said one program by directing said memory controller to transfer said one program from said first memory to the local memory associated with said one first processing unit, said one first processing unit thereafter processing said one program from said local memory.

3. A computer processing system as in claim 1, wherein said one access key comprises a first plurality of bits and said request key associated with said one first processing unit comprises a second plurality of bits, and said memory controller is operable to execute said request only if all of said first plurality of bits match all of said second plurality of bits.

4. A computer processing system as in claim 1, wherein said one access key comprises a first plurality of bits and a key mask and said request key associated with said one first processing unit comprises a second plurality of bits, and said memory controller is operable to execute said request only if all of said first plurality of bits match said second plurality of bits or all bits of said first plurality of bits not matching said second plurality of bits are masked by said key mask.

5. A computer processing system as in claim 1, wherein said one access key comprises a first plurality of bits and said request key associated with said one first processing unit comprises a second plurality of bits and a key mask, and said memory controller is operable to execute said request only if all of said second plurality of bits match said first plurality of bits or all bits of said second plurality of bits not matching said first plurality of bits are masked by said key mask.

6. A computer processing system as in claim 1, wherein each said key entry further includes a key mask.

7. A computer processing system as in claim 1, wherein each said access entry further includes a key mask.

8. A computer processing system as in claim 1, wherein each said key entry further includes a key mask and each said access entry further includes a key mask.

9. A computer processing system as in claim 1, wherein each said access entry further includes a base location entry and a size entry, said base location entry providing the starting address within said first memory of said memory space associated with said access entry and said size entry providing the size within said first memory of said memory space associated with said access entry.

10. A computer processing system as in claim 1, wherein said first memory is a dynamic random access memory and is a main memory for said computer processing system.

11. A computer processing method, said method comprising:

storing in a first memory programs and data associated with said programs;

processing with a plurality of first processing units said programs and said associated data;

controlling with a memory controller accesses to said first memory by said first processing units;

constructing with a second processing unit in a second memory an access table and a key table, said access table comprising a plurality of access entries, each said access entry including an access key and an identification of a memory space within said first memory associated with said access key, said key table comprising a plurality of key entries, each said key entry including an identification of one of said first processing units and a request key associated with said first processing unit;

controlling with said second processing unit said processing of said programs and said associated data by said first processing units;

directing with said second processing unit any one of said first processing units to process one of said programs;

issuing from said one first processing unit, in processing said one program, a request to said memory controller for access to a storage location within said first memory;

comparing, in response to said request, the request key associated with said one first processing unit in said key table with the access keys in said access table;

if one of said access keys corresponds with the request key associated with said one processing unit in said key table and said storage location corresponds to the memory space associated with said one access key identified in said access table, executing said request.

12. A computer processing method as in claim 11, further comprising directing with said second processing unit said one first processing unit to process said one program by issuing from said second processing unit a command to said memory controller to transfer said one program from said first memory to a local memory associated with said one first processing unit, and thereafter processing with said one first processing unit said one program from said local memory.

13. A computer processing method as in claim 11, wherein said one access key comprises a first plurality of bits and said request key associated with said one first processing unit comprises a second plurality of bits, and further comprising executing with said memory controller said request only if all of said first plurality of bits match all of said second plurality of bits.

14. A computer processing method as in claim 11, wherein said one access key comprises a first plurality of bits and a key mask and said request key associated with said one first processing unit comprises a second plurality of bits, and further comprising executing with said memory controller said request only if all of said first plurality of bits match said second plurality of bits or all bits of said first plurality of bits not matching said second plurality of bits are masked by said key mask.

15. A computer processing method as in claim 11, wherein said one access key comprises a first plurality of bits and said request key associated with said one first processing unit comprises a second plurality of bits and a key mask, and further comprising executing with said memory controller said request only if all of said second plurality of bits match said first plurality of bits or all bits of said second plurality of bits not matching said first plurality of bits are masked by said key mask.

16. A computer processing method as in claim 11, wherein each said key entry further includes a key mask.

17. A computer processing method as in claim 11, wherein each said access entry further includes a key mask.

18. A computer processing method as in claim 11, wherein each said key entry further includes a key mask and each said access entry further includes a key mask.

19. A computer processing method as in claim 11, wherein each said access entry further includes a base location entry and a size entry, said base location entry providing the starting address within said first memory of said memory space associated with said access entry and said size entry providing the size within said first memory of said memory space associated with said access entry.

20. A computer processing method as in claim 11, wherein said first memory is a dynamic random access memory and is a main memory for said computer processing system.

21. A computer processing system, said processing system comprising:

a first memory for storing programs and data associated with said programs, said first memory comprising a plurality of addressable storage locations, each said addressable storage location comprising an additional memory segment associated with said addressable storage location and containing an access key for said addressable storage location;

a plurality of first processing units for processing said programs and said associated data;

a memory controller for controlling accesses to said first memory by said first processing units;

a second memory for storing a key table comprising a plurality of key entries, each said key entry including an identification of one of said first processing units and a request key associated with said first processing unit;

a second processing unit for controlling said processing of said programs and said associated data by said first processing units, said second processing unit being operable to assign and maintain said access keys and construct and maintain said key table, said second processing unit being further operable to direct any one of said first processing units to process one of said programs, said one first processing unit being operable in processing said one program to issue a request to said memory controller for access to one of said addressable storage locations, said memory controller being operable, in response to said request, to compare the request key associated with said one processing unit in said key table with the access key contained in the additional memory segment associated with said one addressable storage location, and if the request key associated with said one processing unit in said key table corresponds with said access key contained in said additional memory segment associated with said one addressable storage location, to execute said request.

22. A computer processing system as in claim 21, further comprising a plurality of local memories, each of said local memories being associated with one of said first processing units, and wherein said second processing unit is operable to direct said one first processing unit to process said one program by directing said memory controller to transfer said one program from said first memory to the local memory associated with said one first processing unit, said one first processing unit thereafter processing said one program from said local memory.

23. A computer processing system as in claim 21, wherein said access key contained in said memory segment associated with said one addressable storage location comprises a first plurality of bits and said request key associated with said one first processing unit comprises a second plurality of bits, and said memory controller is operable to execute said request only if all of said first plurality of bits match all of said second plurality of bits.

24. A computer processing system as in claim 21, wherein said access key contained in said memory segment associated with said one addressable storage location comprises a first plurality of bits and a key mask and said request key associated with said one first processing unit comprises a second plurality of bits, and said memory controller is operable to execute said request only if all of said first plurality of bits match said second plurality of bits or all bits of said first plurality of bits not matching said second plurality of bits are masked by said key mask.

25. A computer processing system as in claim 21, wherein said access key contained in said memory segment associated with said one addressable storage location comprises a first plurality of bits and said request key associated with said one first processing unit comprises a second plurality of bits and a key mask, and said memory controller is operable to execute said request only if all of said second plurality of bits match said first plurality of bits or all bits of said second plurality of bits not matching said first plurality of bits are masked by said key mask.

26. A computer processing system as in claim 21, wherein each said key entry further includes a key mask.

27. A computer processing system as in claim 21, wherein each said additional memory segment also contains a key mask.

28. A computer processing system as in claim 21, wherein each said key entry further includes a key mask and each said additional memory segment also contains a key mask.

29. A computer processing system as in claim 21, wherein each said additional memory segment also contains status information regarding the status of data stored in the addressable storage location associated with said additional memory segment.

30. A computer processing system as in claim 21, wherein said first memory is a dynamic random access memory and is a main memory for said computer processing system.

31. A computer processing method, said method comprising:

storing in a first memory programs and data associated with said programs, said first memory comprising a plurality of addressable storage locations, each said addressable storage location including an additional memory segment associated with said addressable storage location;

storing in each said additional memory segment for each said addressable storage location an access key for said addressable storage location;

processing with a plurality of first processing units said programs and said associated data;

controlling with a memory controller accesses to said first memory by said first processing units;

storing in a second memory a key table comprising a plurality of key entries, each said key entry including an identification of one of said first processing units and a request key associated with said first processing unit;

controlling with a second processing unit said processing of said programs and said associated data by said first processing units;

assigning with said second processing unit each said access key;

constructing with said second processing unit said key table;

directing with said second processing unit any one of said first processing units to process one of said programs;

issuing from said one first processing unit, in processing said one program, a request to said memory controller for access to one of said addressable storage locations;

comparing, in response to said request, the request key associated with said one processing unit in said key table with the access key contained in the additional memory segment associated with said one addressable storage location;

if the request key associated with said one processing unit in said key table corresponds with said access key contained in said additional memory segment associated with said one addressable storage location, executing said request.

32. A computer processing method as in claim 31, further comprising directing with said second processing unit said one first processing unit to process said one program by directing said memory controller to transfer said one program from said first memory to the local memory associated with said one first processing unit, and thereafter processing with said one first processing unit said one program from said local memory.

33. A computer processing method as in claim 31, wherein said access key contained in said additional memory segment associated with said one addressable storage location comprises a first plurality of bits and said request key associated with said one first processing unit comprises a second plurality of bits, and further comprising executing with said memory controller said request only if all of said first plurality of bits match all of said second plurality of bits.

34. A computer processing method as in claim 31, wherein said access key contained in said additional memory segment associated with said one addressable storage location comprises a first plurality of bits and a key mask and said request key associated with said one first processing unit comprises a second plurality of bits, and further comprising executing with said memory controller said request only if all of said first plurality of bits match said second plurality of bits or all bits of said first plurality of bits not matching said second plurality of bits are masked by said key mask.

35. A computer processing method as in claim 31, wherein said access key contained in said additional memory segment associated with said one addressable storage location comprises a first plurality of bits and said request key associated with said one first processing unit comprises a second plurality of bits and a key mask, and further comprising executing with said memory controller said request only if all of said second plurality of bits match said first plurality of bits or all bits of said second plurality of bits not matching said first plurality of bits are masked by said key mask.

36. A computer processing method as in claim 31, wherein each said key entry further includes a key mask.

37. A computer processing method as in claim 31, wherein each said additional memory segment also contains a key mask.

38. A computer processing method as in claim 31, wherein each said key entry further includes a key mask and each said additional memory segment also contains a key mask.

39. A computer processing method as in claim 31, wherein each said additional memory segment also contains status information regarding the status of data stored in the addressable storage location associated with said additional memory segment.

40. A computer processing method as in claim 31, wherein said first memory is a dynamic random access memory and is a main memory for said computer processing system.