Memory hub with internal cache and/or memory access prediction
First Claim
1. A memory hub, comprising:
- a memory access device interface structured to interface with a memory access device;
a plurality of memory interfaces structured to interface with respective memory devices, each of the memory interfaces including a memory controller and a memory cache; and
a switch coupling the memory access device interface to each of the memory interfaces.
2 Assignments
0 Petitions
Accused Products
Abstract
A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.
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Citations
39 Claims
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1. A memory hub, comprising:
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a memory access device interface structured to interface with a memory access device;
a plurality of memory interfaces structured to interface with respective memory devices, each of the memory interfaces including a memory controller and a memory cache; and
a switch coupling the memory access device interface to each of the memory interfaces. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory hub, comprising:
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a memory access device interface structured to interface with a memory access device;
a plurality of memory interfaces structured to interface with respective memory devices, each of the memory interfaces including a memory controller and a prediction unit structured to predict an address from which data are likely to be read based on an address from a prior memory access and to cause the memory controller in the respective memory interface to output signals indicative of a memory read operation from the predicted address; and
a switch coupling the memory access device interface to the memory interfaces. - View Dependent Claims (10, 11, 12, 13)
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14. A computer system, comprising:
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a processing unit operable to perform computing functions;
a system controller coupled to the processing unit;
at least one input device coupled to the processing unit through the system controller;
at least one output device coupled to the processing unit through the system controller;
at least one data storage devices coupled to the processing unit through the system controller;
a plurality of memory devices; and
a memory hub comprising;
a processor interface coupled to the processor;
a plurality of memory interfaces coupled to respective ones of the memory devices, each of the memory interfaces including a memory controller and a memory cache; and
a switch coupling the processor interface to each of the memory interfaces. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A computer system, comprising:
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a processing unit operable to perform computing functions;
a system controller coupled to the processing unit;
at least one input device coupled to the processing unit through the system controller;
at least one output device coupled to the processing unit through the system controller;
at least one data storage devices coupled to the processing unit through the system controller;
a plurality of memory devices; and
a memory hub comprising;
a processor interface coupled to the processor;
a plurality of memory interfaces coupled to respective ones of the memory devices, each of the memory interfaces including a memory controller and a prediction unit structured to predict an address from which data are likely to be read based on an address from a prior memory access and to cause the memory controller in the respective memory interface to output to the memory device to which the memory interface is coupled signals indicative of a memory read operation from the predicted address; and
a switch coupling the processor interface to each of the memory interfaces. - View Dependent Claims (26, 27, 28, 29, 30, 31)
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32. A method of accessing a plurality of memory devices, comprising:
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directing a memory access request to a first of a plurality of memory devices coupled to memory hub;
storing data read from or written to the first memory device in a cache memory located in the memory hub;
subsequently directing a memory read request to the first memory device;
in response to the memory read request, detecting whether the data corresponding to the memory read request are stored in the cache memory located in the memory hub;
if the data corresponding to the memory read request are determined to be stored in the cache memory located in the memory hub, providing the read data from the cache memory; and
if the data corresponding to the memory read request are determined to be not stored in the cache memory located in the memory hub, providing the read data from the first memory device. - View Dependent Claims (33, 34, 35, 36)
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37. A method of accessing a plurality of memory devices, comprising:
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directing memory access requests to respective addresses in a plurality of memory devices coupled to memory hub;
within the memory hub, predicting at least one address from which data are likely to be read from the first memory device based on the addresses to which the memory access requests were directed; and
providing respective read data from the predicted addresses in the memory devices prior to receiving memory read requests directed to the predicted addresses. - View Dependent Claims (38, 39)
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Specification