Variable clocked scan test circuitry and method

• US 20030229834A1
• Filed: 01/24/2003
• Published: 12/11/2003
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: American Patents LLC
• Original Assignee: On-chip Technologies, Inc.
• Inventors: Cooke, Laurence H.
• Granted Patent: US 7,234,092 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift clocks required to achieve required values at plurality of scan bit positions, and by using multiple taps from the scan chains to form a check-sum in order to reduce the number of scan shift clocks to capture test results.

Claims

1. A method for testing an integrated circuit comprising steps of;

a) Generating test vectors wherein each said test vector comprise a multiplicity of test-input positions that are set to pre-determined logic values,

b) Loading deterministic values of each said test vector into multiplicity of scan-chains of said integrated circuit by applying serial data and shifting said multiplicity of scan chains,

c) Operating said integrated circuit so that test results are captured in multiplicity of test-response positions of said scan chains,

d) Selecting multiplicity of care-output positions among said test-response positions;

said care-output positions containing test response values for detecting faults that are undetected by previous test vectors,

e) Shifting said multiplicity of scan-chains for at least a minimum number of shift cycles necessary to observe values of said multiplicity of care-outputs at multiplicity of serial output positions in order to determine pass or fail status for each said test vector,

f) Repeating steps (b) through (e) by overlapping operations of step (e) and step (b), until all test vectors are applied.

2. A structure for testing an IC comprising;

g) a multiplicity of Scan_In pins and a multiplicity of Scan_Out pins that carry serial data to and from said structure, respectively,

h) a multiplicity of scan_chain segments, each said scan_chain segment having a serial input pin, a serial output pin and a string of scan elements which are connected output to input such that in one mode of operation said scan_chain segments can be operated to shift data from said serial input pin towards said serial output pin, and

i) a multiplicity of coupling units that couple at least one element in each scan_chain segment and at least one of said Scan In pins to the serial input of next scan_chain segment in sequence, thereby forming a multiplicity of strings of scan_chain segments,

wherein one mode of operation data can be moved serially from said multiplicity of Scan_In pins towards said multiplicity of Scan_Out pins,

3. A structure for independently controlling a multiplicity of clocks comprising;

a common clock,

a common control signal,

a multiplicity of input signals,

a multiplicity of logic functions,

wherein each of said multiplicity of logic functions can be operated by the common clock, common control signal and a single one of said multiplicity of input signals, and generates a single one of said multiplicity of clocks.