Graceful degradation of serial channels

• US 20030229844A1
• Filed: 03/24/2003
• Published: 12/11/2003
• Est. Priority Date: 03/25/2002
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bansal, Akash, Varma, Anujan, Bannur, Jaisimha
• Application Number:
  US10/396,287
• Publication Number:
  US 20030229844A1
• Time in Patent Office: Days
• US Class Current: 714/821
• CPC Class Codes: H04L 69/40 for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection management of faults, events, alarms or notifications in data switching networks H04L41/06

Abstract

In general, in one aspect, the disclosure describes an apparatus that includes a transmission module to split a data segment into a plurality of data stripes and transmit each data strip over an associated serial channel, a reception module to receive the plurality of data stripes over the associated serial channels and track a number of errors per channel, and a controller to deactivate a serial channel and reconfigure said transmission module and said reception module to utilize remaining data channels for striping data if the number of errors in the serial channel exceeds a threshold.

Claims

1. An apparatus, comprising:

a transmission module to split a data segment into a plurality of data stripes and transmit each data strip over an associated serial channel;

a reception module to receive the plurality of data stripes over the associated serial channels and track a number of errors per channel; and

a controller to control the operation of the apparatus, said controller to deactivate a serial channel and reconfigure said transmission module and said reception module to utilize remaining data channels for striping data if the number of errors in the serial channel exceeds a threshold.

2. The apparatus of claim 1, wherein said transmission module generates an error code for each stripe and transmits the error code along with the data stripe.

3. The apparatus of claim 2, wherein the error code is a cyclic redundancy code (CRC).

4. The apparatus of claim 1, wherein said reception module checks for errors by computing an error code for each data stripe and comparing it to a transmitted error code.

5. The apparatus of claim 1, wherein said reception module checks for errors in physical receiving devices for each serial channel.

6. The apparatus of claim 1, wherein said controller reconfigures the apparatus to perform error correction.

7. The apparatus of claim 1, wherein said controller reconfigures said transmission module and said reception module to utilize a subset of the serial channels for data stripes and a subset of the serial channels for parity stripes, wherein the data stripes are organized into at least one group and each group has an associated parity stripe to be utilized for error correction, the parity stripe being generated based on the data stripes within the group.

8. The apparatus of claim 7, wherein said transmission module generates the parity stripe for a group by XORing each of the associated data stripes within the group.

9. The apparatus of claim 7, wherein said reception module recreates a data stripe containing errors based on remaining data stripes and the parity stripes within an associated group, if errors are limited to a single data stripe within the group.

10. The apparatus of claim 9, wherein said reception module recreates the data stripe by XORing each of the other data stripes and the parity stripe within the group.

11. A method, comprising:

dividing a data segment into a plurality of data stripes and associating each data stripe with one of a plurality of serial channels;

transmitting the data stripes from a first card to a second card over the associated serial channels;

receiving the data stripes at the second card;

detecting errors in the data stripes;

tracking number of errors per serial channel; and

deactivating a serial channel and reconfiguring remaining serial channels for striping data if the number of errors in the serial channel exceeds a threshold.

12. The method of claim 11, further comprising creating an error code for each data stripe and appending the error code to the end of the data stripe.

13. The method of claim 12, wherein the error code is a cyclic redundancy code (CRC).

14. The method of claim 11, further comprising computing an error code for the data segment and appending it at the end of the data segment.

15. The method of claim 11, wherein said detecting includes computing an error code for each data stripe and comparing it to a transmitted error code within each data stripe.

16. The method of claim 11, further comprising discarding the data segment if an error is detected.

17. The method of claim 11, further comprising recreating the data segment from the data stripes if no errors are detected.

18. The method of claim 11, wherein a minimum number of serial channels are required to provide an appropriate bandwidth for striping data segments.

19. The method of claim 18, further comprising terminating operation if minimum number of serial channels are not available.

20. The method of claim 11, further comprising

organizing the data stripes into at least one group;

generating a parity stripe for each group based on the data stripes within the group, wherein each parity stripe is utilized for error correction within the group;

associating each parity stripe with one of the serial channels;

transmitting the parity stripes from the first card to the second card over the associated serial channels;

receiving the parity stripes at the second card; and

recreating a data stripe containing errors by utilizing the associated parity stripe, wherein said recreating is limited to a single data stripe per group containing errors.

21. The method of claim 20, wherein said generating includes generating the parity stripe by XORing each of the data stripes within the group.

22. The method of claim 20, wherein said generating includes generating the parity stripe by bitwise XORing each of the data stripes within the group.

23. The method of claim 20, further comprising discarding a data segment if more than one data stripe in a group contains errors.

24. A store and forward device, comprising:

a plurality of interface cards to receive and transmit data;

a backplane connecting the plurality of cards together via a plurality of serial channels;

a transmission module to split a data segment into a plurality of data stripes and transmit each data stripe over an associated serial channel;

a reception module to receive the plurality of data stripes over the associated serial channels and track a number of errors per channel; and

a controller to control the operation of the apparatus, wherein said controller may deactivate a serial channel and reconfigure said transmission module and said reception module to utilize a remaining data channels for striping data if the number of errors in the serial channel exceeds a threshold.

25. The device of claim 24, wherein

said transmission module generates an error code for each stripe and transmits the error code along with the stripe;

and

said reception module checks for errors by computing an error code for each stripe and comparing it to a transmitted error code.

26. The device of claim 24, wherein said controller reconfigures said transmission module and said reception module to utilize a subset of the serial channels for data stripes and a subset of the serial channels for parity stripes, wherein the data stripes are organized into at least one group and each group has an associated parity stripe to be utilized for error correction, the parity stripe being generated based on the data stripes within the group.

27. The device of claim 26, wherein said reception module recreates a data stripe containing errors based on remaining data stripes and the parity stripes within an associated group, if errors are limited to a single data stripe within the group.

28. The device of claim 24, wherein said interface cards are Ethernet cards.

29. The device of claim 24, wherein said backplane is an optical backplane.

30. A computer program product, disposed on a computer readable medium, the program including instructions for causing a processor to:

track a number of errors per serial channel carrying stripes of data segments; and

deactivate a serial channel and reconfigure remaining serial channels for striping data if the number of errors in the serial channel exceeds a threshold.

31. The program of claim 30, further comprising instructions that cause the processor to divide a data segment into stripes for transmission via the serial channels.