Pre-silicon verification path coverage

• US 20030229864A1
• Filed: 06/10/2002
• Published: 12/11/2003
• Est. Priority Date: 06/10/2002
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Watkins, Daniel R.
• Granted Patent: US 6,735,747 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method for verifying a path coverage of a circuit design. The method generally comprises the steps of implementing a hardware description language to include a plurality of monitors for a plurality of nodes of the circuit design, monitoring the nodes of a programmable circuit implementing the circuit design in real-time to capture node data, and assessing the node data to determine the path coverage.

Claims

1. A method for verifying a path coverage of a circuit design, comprising the steps of:

(A) implementing a hardware description language to include a plurality of monitors for a plurality of nodes of said circuit design;

(B) monitoring said nodes of a programmable circuit implementing said circuit design in real-time to capture node data; and

(C) assessing said node data to determine said path coverage.

2. The method according to claim 1, further comprising the steps of:

regression testing an un-instrumented version of said hardware description language to confirm functional operation; and

testing a hardware circuit implementing said circuit design at normal speed using said un-instrumented version of said hardware description language.

3. The method according to claim 1, further comprising the steps of:

compressing said node data in response to said monitoring; and

storing said node data.

4. The method according to claim 3, further comprising the step of uploading said node data prior to assessing.

5. The method according to claim 3, wherein said compressing is (i) scalable and (ii) has a plurality of compressed formats.

6. The method according to claim 5, further comprising the step of assessing candidate changes of said node data for saving prior to said storing.

7. The method according to claim 3, further comprising the step of decompressing said node data prior to said assessing.

8. The method according to claim 1, further comprising the step of limiting said monitoring to a predetermined set of said nodes.

9. The method according to claim 8, wherein the step of assessing comprises the sub-step of generating results for at least one of (i) covered nodes, (ii) not-covered nodes, and (iii) not-monitored nodes.

10. A storage medium for use in a computer, said storage medium recording a computer program comprising the steps of claim 1.

11. An apparatus comprising:

a first tool configured to (i) implement a hardware description language to include a plurality of monitors for a plurality of nodes of a circuit design and (ii) assess node data to determine a path coverage; and

a second tool configured to monitor said nodes of a programmable circuit implementing said circuit design in real-time to capture said node data.

12. The apparatus according to claim 11, further comprising a memory configured to store said node data.

13. The apparatus according to claim 12, further comprising a third tool configured to regulate a usage of said memory based upon a priority list.

14. The apparatus according to claim 12, further comprising a second memory coupled directly to said programmable circuit and configured to temporarily store said node data.

15. The apparatus according to claim 11, wherein said second tool is further configured to trace said nodes at a gate level in real-time.

16. The apparatus according to claim 11, wherein said first tool is further configured to feed a subset of said nodes at a time.

17. The apparatus according to claim 16, wherein said first tool is further configured to blend a plurality of partial path coverage assessments to determine said path coverage.

18. The apparatus according to claim 11, wherein said second tool is further configured to monitor (i) a predetermined node of said nodes from a register field for a change and (ii) at least one path effectuated by said change.

19. The apparatus according to claim 11, wherein said programmable circuit is a field programmable gate array.

20. A method for verifying a path coverage of a circuit design, comprising the steps of:

(A) monitoring a plurality of nodes of a programmable circuit implementing said circuit design in real-time to capture node data;

(B) compressing said node data; and

(C) assessing said node data to determine said path coverage.

21. The method according to claim 20, wherein said step (B) comprises the sub-step of formatting a plurality of changes in said node data into a plurality of compression formats.

22. The method according to claim 21, further comprising the step of assessing said changes for additional processing prior to compressing.

23. The method according to claim 20, further comprising the step of storing said node data in response to compressing.

24. The method according to claim 23, further comprising the step of prioritizing said node data prior to storing.

25. An apparatus comprising:

means for implementing a hardware description language to include a plurality of monitors for a plurality of nodes of said circuit design;

means for monitoring said nodes of a programmable circuit implementing said circuit design in real-time to capture node data; and

means for assessing said node data to determine said path coverage.