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Electronic design for integrated circuits based process related variations

  • US 20030229868A1
  • Filed: 12/17/2002
  • Published: 12/11/2003
  • Est. Priority Date: 06/07/2002
  • Status: Active Grant
First Claim
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1. A method comprising generating an electronic design for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit, the generating including adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model.

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