Electronic design for integrated circuits based process related variations

• US 20030229868A1
• Filed: 12/17/2002
• Published: 12/11/2003
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: White, David, Smith, Taber H.
• Granted Patent: US 7,325,206 B2
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]

Abstract

An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.

Claims

1. A method comprising

generating an electronic design for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit,

the generating including adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model.

2. The method of claim 1 in which the generating also includes using optical proximity correction to adjust the design for optical interference effects.

3. The method of claim 1 in which the electronic design is associated with electrical characteristics that include at least one of sheet resistance, capacitance, drive current, signal integrity, power distribution, and timing closure.

4. The method of claim 1 in which the feature dimension variations are associated with at least one of printed feature widths, etch trench width, etch trench depth, etched sidewall angle, dishing, erosion, or total copper loss.

5. The method of claim 1 also including using a place and route tool to create the electronic design.

6. The method of claim 1 also including using a resistance and capacitance (RC) extraction tool in connection with adjusting the electronic design.

7. The method of claim 1 also including using an electronic design automation simulation tool in connection with creating the electronic design.

8. The method of claim 1 also including verifying the electronic design using a physical verification tool.

9. The method of claim 1 also including adjusting the electronic design based on use of an optical proximity correction (OPC) tool.

10. The method of claim 1 also including verifying the electronic design using a signal integrity tool.

11. The method of claim 1 also including ensuring the manufacturability of the electronic design.

12. The method of claim 1 also including improving the electrical performance of an electronic representation of the integrated circuit.

13. The method of claim 1 also including improving the electrical performance of an electronic design layout of the integrated circuit.

14. The method of claim 1 also including modifying a formatted file based on the adjusting of the electronic design, the file format conforming to a file format used by an EDA tool.

15. The method of claim 14 in which the file format comprises a Graphical Data Stream (GDS) format.

16. The method of claim 1 in which adjusting the electronic design includes improving manufacturability of the integrated circuit.

17. The method of claim 1 in which adjusting the electronic design includes modifying the design to improve circuit performance.

18. The method of claim 1 in which generating the electronic design includes predicting topographical variations with respect to an interconnect level.

19. The method of claim 1 in which generating the electronic design includes predicting topographical variations for multiple levels to electrically characterize or simulate multiple interconnect levels.

20. The method of claim 1 also including determining placement of dummy fill or slotting structures based on the determining of the impact.

21. The method of claim 1 also including determining the placement of electrical components in the integrated circuit.

22. The method of claim 1 also including determining the routing of interconnect regions between electrical components of the integrated circuit.

23. The method of claim 1 in which the integrated circuit comprises a system-on-chip (SoC) device and the method also includes determining the routing of interconnect regions in the SoC device.

24. The method of claim 1 also including determining geometry of electrical features, interconnect lines, or vias in the design of the integrated circuit.

25. The method of claim 1 also including using an electronics design automation (EDA) tool in conjunction with the predicting and the determining.

26. The method of claim 1 in which the generating is provided as a service in a network.

27. The method of claim 26 in which the network comprises an intranet, an extranet, or an internet, and the generating is provided in response to user requests.

28. A method comprising

generating an electronic design for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit,

the generating including adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model, and

using an RC extraction tool in conjunction with generating and adjusting the electronic design.

30. The method of claim 28 or 29 in which the generating is performed on sub-portions of the circuit.

33. The method of claim 28 or 29 in which the generating is provided as a service in a network.

34. The method of claim 33 in which the network comprises an intranet, an extranet, or an internet, and the generating is provided in response to user requests.

29. A method comprising

generating an electronic design for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit,

the generating including adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a patter-dependent model, and

using an RC extraction tool in conjunction with generating and adjusting the electronic design.

31. The method of claim 29 in which the feature dimensions are associated with at least one of printed feature width, etch trench width, etch trench depth, etched sidewall angle, dishing, erosion, or total copper loss.

32. The method of claim 29 in which the electrical characteristics comprise at least one of sheet resistance, capacitance, drive current, signal integrity, power distribution and, timing closure.

35. A method comprising

generating an electronic design for an integrated circuit that is to be fabricated in accordance with a design by a process that will impart feature dimension variations to the integrated circuit,

using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process.

36. A method comprising

using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process, and

determining placement attributes for elements of the integrated circuit based on the predicted characteristics.

37. The method of claim 36 in which the placement attributes comprise attributes of buffer regions for interconnect vias and lines determined during a place and route step in the design.

38. The method of claim 36 in which the predicted characteristics comprise width variation or topographical variation, and the placement attributes comprise the placement locations of electrically active features or components.

39. The method of claim 36 in which the predicted characteristics comprise width variation or geographical variation, and the placement attributes comprise the routing of interconnect features across the integrated circuit.

40. The method of claim 36 in which the predicted characteristics comprise placement of dummy or slotting structures.

41. The method of claim 36 in which the predicted characteristics comprise geometries of dummy or slotting structures.

42. A method comprising

using a pattern-dependent model to predict electrical feature geometries of an integrated circuit that is to be fabricated in accordance with a design by a process, the prediction of electrical feature geometries being based on width variations or topographical variations produced by the process.

43. The method of claim 42 including modifying the design to improve circuit performance of the electrical features.

44. The method claim 42 including modifying the design to improve structural or reliability characteristics of the electrical features.