Use of models in integrated circuit fabrication

• US 20030229875A1
• Filed: 06/07/2002
• Published: 12/11/2003
• Est. Priority Date: 06/07/2002
• Status: Abandoned Application

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: White, David, Smith, Taber H., Mehrotra, Vikas
• Application Number:
  US10/164,842
• Publication Number:
  US 20030229875A1
• Time in Patent Office: Days
• US Class Current: 716/10
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Claims

1. A method comprising

performing pattern dependent modeling and prediction for electrochemical mechanical deposition, chemical vapor deposition of low-K interlayer dielectric, or spin-on of low-K interlayer dielectric.

9. The method of claim 1 also including analyzing electrical impacts.

24. The method of claim 1, 2, 3, 4, or 8 in which the dummy fill generation is performed by a user through a web browser and a server.

25. The method of claim 24 in which the server is local to the user.

26. The method of claim 24 in which the server is remote from the user.

27. The method of claim 24 where dummy fill generation is performed on a server by web services

107. The method of claims 1, 2, 3, 4 or 8 in which the process comprises a damascene process.

108. The method of claim 1, 2, 3, 4, or 8 also comprising enabling a user to obtain a dummy fill strategy for a semiconductor design over the internet using web services.

2. A method comprising

based on electrical impact analysis and a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process, and

using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the dummy fill to be placed,

the use of the model and the electrical impact analysis being embedded as part of the generation of the dummy fill placement strategy.

28. The method of claim 2, 3, 4, or 8 in which the fabrication process comprises an electrochemical mechanical deposition process.

29. The method of claim 2, 3, 4, or 8 in which the strategy for placement of dummy fill includes determining the size and placement of dummy fill.

30. The method of claim 2, 3, 4, or 8 in which the fabrication process comprises a formation of a low-K interlayer dielectric.

32. The method of claim 2, 3, 4, or 8 in which generating the dummy fill strategy includes dividing a semiconductor design into grids.

33. The method of claims 2, 3, 4, or 8 in which generating the dummy fill strategy also includes extracting local pattern densities for a semiconductor design for each of the grids.

34. The method of claim 2, 3, 4, or 8 in which generating the dummy fill strategy also includes extracting local line width for a semiconductor design for each of the grids.

35. The method of claim 2, 3, 4, or 8 in which generating the dummy fill strategy also includes extracting local line spacing for a semiconductor design for each of the grids.

36. The method of claim 35 in which generating the dummy fill strategy also includes computing an effective pattern density for each grid.

37. The method of claim 36 also including using models for computing film thickness non-uniformity with respect to a semiconductor design for which the dummy fill strategy is being generated.

38. The method of claim 37 also including computing a variation in film thickness.

39. The method of claim 32 also including deriving coordinates of all objects within each of the grids.

40. The method of claim 39 also including generating at least one of line width, line space, length, and bounding box with respect to each of the objects.

41. The method of claim 40 in which the dummy fill strategy includes adding dummy fill in empty areas of each of the grids.

42. The method of claim 41 in which the dummy fill includes slots in objects.

43. The method of claim 42 also comprising re-computing a local density in each of the grids after adding dummy fill.

44. The method of claim 42 also comprising re-computing an effective pattern density for each of the grids after adding dummy fill.

45. The method of claim 2, 3, 4, or 8 in which the dummy fill strategy is based on criteria for electrical parameter variation tolerances for at least one of the following:

capacitance and resistance, sheet resistance, outputs delay, skew, voltage drop, drive current loss, dielectric constant or crosstalk noise.

46. The method of claim 44 in which the effective pattern density is computed based on a polishing process planarization length.

47. The method of claim 44 in which the effective pattern density is computed using an elliptically weighted window or other filter.

48. The method of claim 2, 3, 4, or 8 in which a film thickness non-uniformity is based on physical layout parameters.

49. The method of claim 2, 3, 4, or 8 in which the parameters include at least one of density, line width, and/or line space.

50. The method of claim 2, 3, 4, or 8 also comprising using the dummy fill strategy to reduce a variation in or due to electroplated copper deposition before and after chemical mechanical polishing.

51. The method of claim 2, 3, 4, or 8 in which generating the dummy fill strategy is done automatically.

54. The method of claim 2, 3, 4, or 8 in which the fabrication process comprises lithography.

55. The method of claim 2, 3, 4, or 8 in which the fabrication process comprises electrochemical deposition.

56. The method of claim 2, 3, 4, or 8 in which the fabrication process comprises copper chemical mechanical polishing.

57. The method of claim 2, 3, 4, or 8 in which the fabrication process comprises electrochemical mechanical deposition

58. The method of claim 2, 3, 4, or 8 in which the fabrication process includes low-k dielectric materials.

59. The method of claim 2, 3, 4, or 8 in which the fabrication process includes low-k dielectric processes.

60. The method of claims 2, 3, 4, or 8 also including

extracting pattern dependencies from a layout of the semiconductor.

61. The method of claim 60 in which the layout dependencies include with resepect to line spacing, line width or line density.

95. The method of claim 2, 3, 4, or 8 in which the dummy fill placement strategy includes using dummy fill objects to improve a structural integrity of low-K dielectric features.

96. The method of claim 2, 3, 4, or 8 in which the dummy fill placement strategy includes using dummy fill objects to maintain or improve an effective dielectric constant of low-K dielectric features.

97. The method of claim 96 in which the effective dielectric constant is maintained through all steps of a damascene process flow.

98. The method of claim 2, 3, or 4 in which the dummy fill placement strategy includes using dummy fill objects to facilitate integration of low-k dielectric materials into a damascene process flow.

3. A method comprising

based on an electrical impact analysis and a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process, and

using the pattern dependent model and the electrical impact analysis to evaluate the expected results of the dummy fill to be placed,

the fabrication process for which the strategy is being generated comprising other than an oxide chemical mechanical polishing process.

4. A method comprising

based on a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process, and

using the pattern dependent model to evaluate the expected results of the dummy fill to be placed,

the fabrication process for which the strategy is being generated comprising two or more stages of fabrication.

5. The method of claim 4 in which each of the stages comprises a process recipe.

6. The method of claim 4 in which each of the stages comprises a process type.

7. The method of claim 4 in which each of the stages comprises a process flow.

17. The method of claim 4 in which the two stages comprise two or more processes.

18. The method of claim 4 in which the two stages comprise two or more steps of a single process.

19. The method of claim 4 in which the two stages comprise two or more recipes of a single process type.

20. The method of claim 4 in which the two stages comprise two or more processes within a process flow.

21. The method of claim 4 in which the two stages comprise deposition and chemical mechanical polishing.

22. The method of claim 4 in which the generating of a strategy includes generating dummy fill rules.

31. The method of claim 4 in which one of the fabrication processes comprises chemical vapor deposition or spin-on of the low-K dielectric.

52. The method of claim 22 in which dummy fill rules based on electrical design guidelines are generated dynamically with a change in technology or design parameters.

53. The method of claim 22 in which an effective pattern density is generated dynamically with a change in a process planarization length.

8. A method comprising

based on a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process, and

using the pattern dependent model to evaluate the expected results of the dummy fill to be placed,

the fabrication process for which the strategy is being generated comprising a polishing or planarization process in which more than one material is removed.

10. A method comprising

operating a server to provide dummy fill generation functions for a semiconductor design, and

enabling a user at a client to operate through a web browser to use the dummy fill placement functions.

11. The method of claim 10 in which the server is local to the user.

12. The method of claim 10 in which the server is remote from the user.

13. The method of claim 10 in which the dummy fill placement functions are used with respect to at least one of the following processes:

electrochemical mechanical deposition, chemical vapor deposition, spin-on, lithography, electrochemical deposition, chemical mechanical polishing.

14. The method of claim 10 in which the dummy fill placement functions are used with respect to shallow trench isolation.

15. The method of claim 10 in which the dummy fill placement functions are used with respect to oxide layer dielectric.

16. A method comprising

using a pattern dependent model to analyze an integrated circuit design,

applying a dummy fill strategy to the design

analyzing the design to which the dummy fill strategy has been applied,

adjusting the design based on the analysis,

iterating the analyzing and adjusting steps, and

certifying that that a integrated circuit manufactured according to the adjusted design will be within predefined physical and electrical parameters.

23. A method comprising

defining a set of hierarchical cell placements for dummy fill for a semiconductor fabrication process, and

reducing a size of an electronic layout file to which dummy fill is added by using the hierarchical cell placements.

62. A method comprising

using patterned test wafers or test semiconductor devices to calibrate a pattern dependent model with respect to a preselected tool or process recipe, and

based on a pattern dependent model of a semiconductor fabrication process, generating a strategy for placement of dummy fill in the process.

63. A method comprising

generating full-chip pattern dependent models for at least one of the following processes:

electrochemical deposition, electrochemical mechanical deposition, copper chemical mechanical polishing, lithography, shallow trench isolation chemical mechanical polishing, chemical vapor deposition low-K interlayer dielectric, spin-on low-K interlayer dielectric, and

based on the pattern dependent model, generating a strategy for placement of dummy fill in the process.

64. A method comprising

using a calibrated pattern dependent model to map pattern dependent features to wafer-state parameters such as resulting film thickness, film thickness variation, dishing, erosion and electrical parameters such as sheet resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, dielectric constant, and effective dielectric constant, and

based on the pattern dependent model, generating a strategy for placement of dummy fill in a fabrication process.

65. A method comprising

based on a pattern dependent model, generating a strategy for placement of dummy fill in a process, and

using a cost function to measure an impact of dummy fill modification on process induced wafer state and electrical parameter variation.

66. A method comprising

based on a combination of more than one pattern dependent model, generating a strategy for placement of dummy fill in a process, and

predicting an impact of the dummy fill generated by the strategy on process variation.

67. A method comprising

based on a combination of more than one pattern dependent model and cost function, generating a strategy for placement of dummy fill in a process that optimizes full-chip wafer-state and electrical parameters

68. A method comprising

based on predicted or simulated wafer state and electrical parameters, generating dummy fill rules for use in dummy fill placement in a semiconductor fabrication process.

69. The method of claim 68 in which the dummy fill rules include dummy fill sizing.

70. The method of claim 68 in which the dummy fill rules include dummy fill placement.

71. The method of claim 68 in which the dummy fill rules include dummy fill hierarchical cell creation and management.

72. A method comprising

providing dummy fill functions to generate dummy fill for a semiconductor fabrication process, and

using the functions to automatically modify GDS-format electronic layout files for a semiconductor device.

93. The method of claim 72 in which the GDS files are modified to improve uniformity and electrical performance of the semiconductor device.

94. The method of claim 93 in which the process comprises a damascene process flow.

73. A method comprising

at a server, receiving from a client layout file for a semiconductor device,

generating dummy fill modifications to the layout file at the server, and

returning the dummy fill modified layout file from the server to the client.

74. The method of claim 73 in which the server and client communicate using the internet.

75. The method of claim 73 in which the server and client communicate using an extranet.

76. The method of claim 73 in which the server and client communicate using an intranet.

77. The method of claim 73 in which the server and client communicate using a virtual private network (VPN).

78. The method of claim 73 in which the server and client use Secure Shell (SSH) secure communication protocols.

79. The method of claim 73 in which the server and client use Secure Socket Layers (SSL) secure communication protocols.

80. The method of claim 73 in which the server and client use Virtual Private Network (VPN) secure communication protocols.

81. A method comprising

at a web server, providing a service that enables a user to interactively configure a dummy fill application running on the server, and

enabling the user to generate dummy fill information using the dummy fill application.

82. The method of claim 81 where the user is at a remote location with regard to the server.

83. A method comprising

making available to a user on a network a service that enables the user to verify dummy fill information with respect to a semiconductor design and a fabrication process.

84. The method of claim 83 in which the dummy fill information that is verified includes at least one of a dummy fill pattern, a dummy fill strategy, or a dummy fill representation.

85. The method of claim 83 in which the dummy fill information is verified with respect to a single interconnect level of the semiconductor design.

86. The method of claim 83 in which the dummy fill information is verified with respect to multiple interconnect levels of the semiconductor design.

87. The method of claim 83 also including sizing dummy fill objects and creating a dummy fill pattern of the objects for one or more interconnect levels of the semiconductor design.

88. The method of claim 83 in which the dummy fill information comprises dummy fill rules.

89. The method of claim 83 in which the pattern includes oxide or metal dummy fill objects.

90. The method of claim 83 in which the objects of the dummy fill pattern are placed to minimize full-chip film thickness variation.

91. The method of claim 83 in which the objects of the dummy fill pattern are placed to minimize full-chip variation in electrical parameters.

92. The method of claim 91 in which the electrical parameters comprise at least one of sheet resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, dielectric constant, and effective dielectric constant.

99. A medium bearing information capable of configuring a machine to enable a user to search for and retrieve information comprising sizes of dummy fill objects to be included in semiconductor device designs.

100. A medium bearing information capable of configuring a machine to enable a user to search for and retrieve information comprising libraries of dummy fill objects or patterns.

101. A medium bearing information capable of configuring a machine to enable a user to search for and retrieve information comprising libraries of dummy fill rules.

102. A method comprising

maintaining a library of semiconductor dummy fill information, and

making the library available for use in connection with generating dummy fill placement specifications, and

updating the library with changed dummy fill information.

103. A method comprising

storing calibration information with respect to at least one of the following:

process tools, recipes, and flows, and

updating the calibration information to reflect changes in the process tools, recipes or flows.

104. The method of claim 103 also including using the calibration information in generating a dummy fill strategy.

105. The method of claim 103 also including selecting among process tools, recipes and flows from calibration database based upon desired dummy fill characteristics.

106. A method comprising

enabling a user to obtain a dummy fill strategy for a semiconductor design using a single click of a user interface device through a user interface.