Test masks for lithographic and etch processes

• US 20030229880A1
• Filed: 12/17/2002
• Published: 12/11/2003
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: White, David, Smith, Taber H.
• Granted Patent: US 7,243,316 B2
• Time in Patent Office: Days
• US Class Current: 716/19
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]

Abstract

A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.

Claims

1. A method comprising

generating a mask design for patterning a test wafer using a lithographic or etch process,

characterizing the process based on the patterned test wafer, and

using a pattern-dependent model based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.,

2. The method of claim 1 in which the mask design comprises various line and space dimensions.

3. The method of claim 1 in which the mask design includes multiple masks for multiple levels, each of the masks including various line and space dimensions.

4. The method of claim 1 in which the process comprises a preselected lithography or etch tool or lithography or etch recipe.

5. The method of claim 1 in which the process comprises preselected power settings.

6. The method of claim 1 in which the process comprises preselected etch times.

7. The method of claim 1 in which the process comprises preselected polish times.

8. The method of claim 1 in which the process comprises preselected deposition times.

9. The method of claim 1 in which the process comprises preselected pressures.

10. The method of claim 1 also including using an electronics design automation (EDA) tool in conjunction with at least one of the generating, the characterizing, and the predicting.

11. The method of claim 1 in which at least one of the generating, the characterizing, and the predicting is provided as a service in a network.

12. The method of claim 11 in which the network comprises an intranet, an extranet, or an internet, and the generating, the characterizing, and the predicting is provided in response to user requests.

13. The method of claim 1 in which the recipe includes a preselected photoresist.