Semiconductor device assemblies and packages including multiple semiconductor devices and methods

• US 20030230801A1
• Filed: 06/27/2002
• Published: 12/18/2003
• Est. Priority Date: 06/27/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jiang, Tongbi, Chye, Lim Thiam, Yean, Tay Wuu, Fee, Setho Sing
• Granted Patent: US 6,906,415 B2
• Time in Patent Office: Days
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85424 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85439 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1064 : Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/045 : Hierarchy auxiliary PCB, i.e. more than two levels of hierarchy for daughter PCBs are important
• CPC Class Codes: H05K 2201/049 : PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/09181 : Notches in edge pads
• CPC Class Codes: H05K 2201/10727 : Leadless chip carrier [LCC], e.g. chip-modules for cards
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3442 : having edge contacts, e.g. leadless chip capacitors, chip carriers
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence

Abstract

A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

Claims

1. A semiconductor device assembly, comprising:

an interposer including at least one receptacle configured to at least partially receive a semiconductor device formed therein;

at least one semiconductor device positioned at least partially within and at least partially laterally confined within said at least one receptacle; and

at least another semiconductor device at least partially superimposed over said at least one semiconductor device and at least partially supported by said interposer.

2. The semiconductor device assembly of claim 1, wherein said at least one receptacle extends substantially through said interposer.

3. The semiconductor device assembly of claim 1, wherein said at least one semiconductor device is completely laterally surrounded by said interposer.

4. The semiconductor device assembly of claim 1, wherein active surfaces of said at least one semiconductor device and said at least another semiconductor device face in substantially the same direction.

5. The semiconductor device assembly of claim 4, further comprising:

at least one intermediate conductive element extending laterally between and electrically connecting a bond pad of said at least one semiconductor device to a corresponding contact area of said interposer; and

at least another intermediate conductive element extending laterally between and electrically connecting a bond pad of said at least another semiconductor device and another corresponding contact area of said interposer.

6. The semiconductor device assembly of claim 5, wherein said corresponding contact area and said another corresponding contact area are located on the same surface of said interposer.

7. The semiconductor device assembly of claim 4, wherein said at least another semiconductor device includes at least one redistribution circuit on a surface thereof.

8. The semiconductor device assembly of claim 7, further comprising:

at least one discrete conductive element electrically connecting a bond pad of said at least one semiconductor device and a portion of said at least one redistribution circuit in alignment with said bond pad; and

at least another discrete conductive element electrically connecting another portion of said at least one redistribution circuit and a corresponding contact area of said interposer in alignment with said another portion.

9. The semiconductor device assembly of claim 8, wherein said at least one redistribution circuit is carried upon a back side of said at least another semiconductor device.

10. The semiconductor device assembly of claim 9, further comprising:

at least one intermediate conductive element extending laterally between and electrically connecting a bond pad on said active surface of said at least another semiconductor device and another corresponding contact area of said interposer.

11. The semiconductor device assembly of claim 8, wherein said at least one redistribution circuit is carried upon said active surface of said at least another semiconductor device.

12. The semiconductor device assembly of claim 11, further comprising:

at least another discrete conductive element electrically connecting a bond pad on said active surface of said at least another semiconductor device and another corresponding contact area of said interposer in substantial alignment with said bond pad.

13. The semiconductor device assembly of claim 1, wherein active surfaces of said at least one semiconductor device and said at least another semiconductor device face one another.

14. The semiconductor device assembly of claim 13, further comprising:

at least one discrete conductive element extending between and electrically connecting a bond pad of said at least one semiconductor device and a corresponding bond pad of said at least another semiconductor device in substantially alignment with said bond pad; and

at least another discrete conductive element extending between and electrically connecting another bond pad of said at least another semiconductor device and a corresponding contact area of said interposer in substantial alignment with said another bond pad.

15. The semiconductor device assembly of claim 14, wherein said corresponding bond pad of said at least another semiconductor device comprises a portion of a redistribution circuit on said active surface of said at least another semiconductor device.

16. The semiconductor device assembly of claim 15, wherein said redistribution circuit further comprises a circuit trace in communication with said corresponding bond pad and a redistribution bond pad at an opposite end of said circuit trace.

17. The semiconductor device assembly of claim 16, wherein said another bond pad of said at least another semiconductor device comprises said redistribution bond pad.

18. The semiconductor device assembly of claim 13, comprising at least two semiconductor devices positioned at least partially within said at least one receptacle.

19. The semiconductor device assembly of claim 18, wherein back sides of said at least two semiconductor devices face one another.

20. The semiconductor device assembly of claim 19, wherein another semiconductor device is positioned adjacent to an active surface of each of said at least two semiconductor devices.

21. The semiconductor device assembly of claim 1, wherein:

circuitry of said at least another semiconductor device is in electrical communication with corresponding circuitry of said interposer; and

circuitry of said at least one semiconductor device is in electrical communication with corresponding circuitry of at least one of said at least another semiconductor device and said interposer.

22. The semiconductor device assembly of claim 21, further comprising:

a quantity of underfill material between at least peripheral edges of said at least one semiconductor device and surfaces of said at least one receptacle.

23. The semiconductor device assembly of claim 22, wherein said underfill material is located between adjacent surfaces of said at least one semiconductor device and said at least another semiconductor device.

24. The semiconductor device assembly of claim 21, further comprising:

encapsulant material covering at least a peripheral edge of said at least another semiconductor device and adjacent regions of said interposer.

25. The semiconductor device assembly of claim 21, further comprising:

conductive structures on said interposer for electrical connection of said interposer to a higher-level substrate.

26. The semiconductor device assembly of claim 25, wherein said conductive structures comprise contact pads on a surface of said interposer and discrete conductive elements that protrude from said surface of said interposer.

27. The semiconductor device assembly of claim 26, wherein said discrete conductive elements protrude from an opposite surface from that by which said at least another semiconductor device is at least partially supported.

28. The semiconductor device assembly of claim 26, wherein said discrete conductive elements protrude from the same surface as that by which said at least another semiconductor device is at least partially supported.

29. The semiconductor device assembly of claim 26, wherein said discrete conductive elements comprise at least one of balls, bumps, columns, pillars, and pins of conductive material.

30. The semiconductor device assembly of claim 1, wherein said interposer includes:

first contact pads on a first surface thereof for establishing electrical communication between circuitry of said interposer or a semiconductor device supported thereby and a higher-level substrate; and

second contact pads on a second surface thereof, opposite said first surface, for establishing electrical communication between said circuitry of said interposer or said semiconductor device supported thereby and another semiconductor device assembly at least partially superimposed over said interposer.

31. A semiconductor device assembly, comprising:

an interposer including a first surface, a second surface opposite said first surface, and at least one receptacle extending from said first surface to said second surface;

a first semiconductor device positioned at least partially adjacent to said first surface and including an active surface, at least a portion of which faces said at least one receptacle;

at least one first discrete conductive element electrically connecting a′

bond pad of said first semiconductor device and a corresponding contact pad at said first surface of said interposer that is in substantial alignment with said bond pad;

a second semiconductor device positioned at least partially adjacent to said second surface and including an active surface, at least a portion of which faces said at least one receptacle; and

at least one second discrete conductive element electrically connecting a bond pad of said second semiconductor device and a corresponding bond pad of said first semiconductor device through said at least one receptacle.

32. The semiconductor device assembly of claim 31, wherein said at least one second discrete conductive element comprises at least one of a ball, bump, column, pillar, and pin.

33. The semiconductor device assembly of claim 31, wherein said corresponding bond pad comprises a portion of a redistribution circuit on said active surface of said first semiconductor device.

34. The semiconductor device assembly of claim 33, wherein said redistribution circuit further comprises a conductive trace in electrical communication with said corresponding bond pad and a redistribution bond pad at an end of said conductive trace opposite from said corresponding bond pad.

35. The semiconductor device assembly of claim 34, wherein said redistribution bond pad is positioned adjacent to an outer periphery of said second semiconductor device.

36. A multidie semiconductor device package, comprising:

an interposer, comprising;

a substrate with upper and lower surfaces;

a receptacle extending between said upper and lower surfaces; and

electrical conductors on at least said upper surface;

at least one first-level semiconductor device positioned within said receptacle, each said at least one first-level semiconductor device having an active surface;

a second-level semiconductor device positioned above said upper surface of said substrate and attached thereto, said second-level semiconductor device having an active surface; and

electrical connections connecting said at least one first-level semiconductor device and said second-level semiconductor device to said electrical conductors.

37. The multidie semiconductor device package of claim 36, further comprising outer connectors for attaching said multidie semiconductor device package to conductors on an object.

38. The multidie semiconductor device package of claim 37, wherein said outer connectors are mounted on said lower surface of said substrate and conductively connected to said electrical conductors.

39. The multidie semiconductor device package of claim 38, wherein said outer connectors are conductively connected to said electrical conductors by conductive vias extending between said upper surface and said lower surface of said substrate.

40. The multidie semiconductor device package of claim 37, wherein said object comprises one of a circuit board and another semiconductor device package.

41. The multidie semiconductor device package of claim 37, wherein said outer connectors comprise one of conductive balls, conductive bumps, conductive columns, conductive pins and plug-in type electrical connectors.

42. The multidie semiconductor device package of claim 36, wherein said second-level semiconductor device has a larger footprint than that of said at least one first-level semiconductor device.

43. The multidie semiconductor device package of claim 36, wherein said second-level semiconductor device is larger than said receptacle in at least one of an X and Y dimension.

44. The multidie semiconductor device package of claim 36, wherein said electrical connections connecting said at least one first-level semiconductor device to said electrical conductors comprise elongate, intermediate conductive elements.

45. The multidie semiconductor device package of claim 36, wherein said electrical connections connecting said second-level semiconductor device to said electrical conductors comprise elongate, intermediate conductive elements.

46. The multidie semiconductor device package of claim 36, wherein said electrical connections connecting said second-level semiconductor device to said electrical conductors comprise discrete conductive elements interposed between said active surface of said second-level semiconductor device and said electrical conductors.

47. The multidie semiconductor device package of claim 46, wherein said electrical connections connecting said second-level semiconductor device to said electrical conductors comprise one of conductive balls, conductive bumps, conductive pins, conductive columns, conductive pillars, and conductive regions of z-axis conductive or conductor-filled elastomer.

48. The multidie semiconductor device package of claim 46, wherein bond pads of said at least one first-level semiconductor device are connected to corresponding bond pads on said active surface of said second-level semiconductor device by first-level electrical connections.

49. The multidie semiconductor device package of claim 48, wherein said first-level electrical connections between said bond pads of said at least one first-level semiconductor device and said corresponding bond pads of said second-level semiconductor device comprise one of conductive balls, conductive bumps, conductive pins, conductive columns, conductive pillars and conductive regions of z-axis conductive or conductor-filled elastomer.

50. The multidie semiconductor device package of claim 46, wherein said second-level semiconductor device is attached to said upper surface of said substrate of said interposer.

51. The multidie semiconductor device package of claim 36, wherein a back side of said at least one first-level semiconductor device is substantially coplanar with said lower surface of said substrate.

52. The multidie semiconductor device package of claim 36, further comprising a third-level semiconductor device with an active surface, bond pads on said active surface of said third-level semiconductor device being attached by conductive connectors to said lower surface of said substrate.

53. The multidie semiconductor device package of claim 52, wherein said conductive connectors on said third-level semiconductor device comprise one of conductive balls, conductive bumps, conductive pins, conductive columns, conductive pillars, conductive regions of z-axis conductive or conductor-filled elastomer, bond wires, conductive tape-automated bonding elements, and leads.

54. The multidie semiconductor device package of claim 52, further comprising a second first-level semiconductor device positioned below said at least one first-level semiconductor device in said receptacle, said second first-level semiconductor device electrically attached to said third-level semiconductor device in a flip-chip arrangement.

55. The multidie semiconductor device package of claim 36, wherein said at least one first-level semiconductor device comprises a plurality of first-level semiconductor devices mounted side-by-side in said receptacle.

56. A method for assembling a multidie semiconductor device package, comprising:

providing an interposer with a substantially planar substrate and a receptacle formed substantially through said substrate, said substrate having an upper surface and a lower surface, at least said upper surface having conductors thereon;

positioning at least one first-level semiconductor device within said receptacle, an interstitial space remaining at least between peripheral edges of said at least one first-level semiconductor device and said substrate;

positioning a second-level semiconductor device above said upper surface of said substrate;

electrically connecting said at least one first-level semiconductor device to at least one of said conductors on said upper surface of said substrate and said second-level semiconductor device by first-level conductive members; and

electrically connecting said second-level semiconductor device to said conductors on said upper surface of said substrate by second-level conductive members.

57. The method of claim 56, further comprising introducing a quantity of encapsulant material into said receptacle so as to fill at least a portion of said interstitial space.

58. The method of claim 56, wherein said introducing encapsulant material is effected after said electrically connecting said at least one first-level semiconductor device.

59. The method of claim 57, further comprising introducing a quantity of encapsulant material between said second-level semiconductor device and said at least one first-level semiconductor device.

60. The method of claim 56, wherein said electrically connecting said at least one first-level semiconductor device comprises forming or positioning intermediate conductive elements between bond pads of said at least one first-level semiconductor device and corresponding conductors of said interposer.

61. The method of claim 56, wherein said electrically connecting said second-level semiconductor device comprises forming or positioning intermediate conductive elements between bond pads of said second-level semiconductor device and corresponding conductors of said interposer.

62. The method of claim 56, wherein said positioning said second-level semiconductor device comprises at least one of positioning said second-level semiconductor device in a flip-chip arrangement over said at least one first-level semiconductor device and positioning said second-level semiconductor device over said interposer.

63. The method of claim 62, wherein said at least one first-level semiconductor device and said second-level semiconductor device are secured to one another before said positioning said second-level semiconductor device.

64. The method of claim 56, wherein said providing an interposer comprises providing a multi-interposer substrate on which said at least one first-level semiconductor device and said second-level semiconductor device are positioned and electrically connected.

65. The method of claim 64, further comprising singulating individual assemblies or packages from said multi-interposer substrate.

66. The method of claim 57, further comprising adhering a film to said lower surface of said substrate to cover at least a portion of said receptacle prior to positioning said at least one first-level semiconductor device therein.

67. The method of claim 66, further comprising removing said adhered film from said lower surface following curing of said encapsulant in said receptacle.