Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assemblies and packages including such semiconductor devices or packages and associated methods

• US 20030230802A1
• Filed: 07/17/2002
• Published: 12/18/2003
• Est. Priority Date: 06/18/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeung, Boon Suan, Poo, Chia Yong, Loo, Neo Yong, Kwang, Chua Swee, Waf, Low Siu, Yu, Chan Min
• Granted Patent: US 6,818,977 B2
• Time in Patent Office: Days
• US Class Current: 257/734
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/045 Hierarchy auxiliary PCB, i.e. more than two levels of hierarchy for daughter PCBs are important
• CPC Class Codes: H05K 2201/049 PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/09181 Notches in edge pads
• CPC Class Codes: H05K 2201/10727 Leadless chip carrier [LCC], e.g. chip-modules for cards
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/3442 having edge contacts, e.g. leadless chip capacitors, chip carriers
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence

Abstract

A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

Claims

1. A module including a plurality of semiconductor devices in stacked arrangement comprising:

a first function level comprising;

a first semiconductor device including a first pattern of outer connectors exposed at a peripheral edge thereof; and

a carrier substrate underlying said first semiconductor device and including conductive sites arranged correspondingly to said first pattern and electrically connected thereto;

a second function level comprising;

a second semiconductor device including a second pattern of outer connectors exposed at a peripheral edge thereof; and

a first intermediate substrate underlying said second semiconductor device and at least partially overlying said first semiconductor device, said first intermediate substrate including conductive connectors, at least some of which are arranged in a third pattern and positioned along a peripheral edge of said first intermediate substrate, said third pattern conforming at least partially to said first pattern; and

others of which conductive connectors are arranged in a fourth pattern and positioned along a peripheral edge of said first intermediate substrate, said third pattern conforming at least partially to said second pattern, conductive connectors of said first intermediate substrate being electrically connected to corresponding outer connectors of said first and second patterns.

2. The module of claim 1, further comprising at least one additional function level comprising a third semiconductor device and a second intermediate substrate.

3. The module of claim 2, comprising a plurality of additional, stacked function levels.

4. The module of claim 1, further comprising conductive elements that electrically connect outer connectors to one another, to conductive connectors of said first intermediate substrate, and to said conductive sites of said carrier substrate.

5. The module of claim 4, wherein said conductive elements comprise solder.

6. The module of claim 4, wherein said conductive elements comprise gang bonds.

7. The module of claim 1, wherein said first semiconductor device and said second semiconductor device have different outer connector pitches.

8. The module of claim 1, wherein each of said outer connectors comprises a semicylindrical indentation extending along a height of a corresponding peripheral edge of a corresponding semiconductor device.

9. The module of claim 8, wherein said outer connectors comprise one of a metal, a metal alloy, and a nonmetal conductive material.

10. The module of claim 8, wherein said outer connectors comprise copper.

11. The module of claim 1, wherein said first intermediate substrate comprises a rigid structure.

12. The module of claim 11, wherein said rigid structure comprises a resin.

13. The module of claim 12, wherein said resin comprises one of epoxy, polyimide, polytetrafluoroethylene, cyanate ester, FR-4s, and bismaleimide triazine.

14. The module of claim 1, wherein said first intermediate substrate comprises a flexible structure.

15. The module of claim 14, wherein said flexible structure comprises a polyimide film.

16. The module of claim 1, further comprising an array of module connectors extending from said carrier substrate for establishing electrical communication between conductive sites of said carrier substrate and a higher-level substrate.

17. The module of claim 16, wherein said array of module connectors comprises one of a ball-grid-array, a pin-grid-array, columns, leadless chip carrier connectors, and dual in-line connectors.

18. A semiconductor device assembly, comprising:

a first semiconductor device including an active surface, a back side, and a first set of castellated connectors on at least one peripheral edge thereof, castellated connectors of said first set extending substantially from said active surface to said back side;

a second semiconductor device including an active surface, a back side, and a second set of castellated connectors on at least one peripheral edge thereof, castellated connectors of said second set extending substantially from said active surface of said second semiconductor device to said back side of said second semiconductor device;

an intermediate substrate including a third set of castellated connectors on at least one peripheral edge thereof, said third set of castellated connectors having substantially the same pitch as said first set, corresponding connectors of said first and third sets in electrical communication with one another; and

a fourth set of conductive connection sites on a surface of said intermediate substrate, said fourth set of conductive connection sites having substantially the same pitch as corresponding castellated connectors of said second set, corresponding castellated connectors of said second set and corresponding conductive connection sites of said fourth set in electrical communication with one another, said intermediate substrate also including conductive traces electrically connecting corresponding castellated connectors of said third set and corresponding conductive connection sites of said fourth set.

19. The semiconductor device assembly of claim 18, wherein said second set of castellated connectors has a different pitch from that of said first set of castellated connectors.

20. The semiconductor device assembly of claim 18, wherein at least some castellated connectors of said first, second, and third sets comprise a semicylindrically shaped recess extending substantially a height of each said castellated connector.

21. The semiconductor device assembly of claim 18, wherein corresponding castellated connectors are secured to one another with solder.

22. The semiconductor device assembly of claim 18, wherein said intermediate substrate is substantially coextensive with said first semiconductor device.

23. The semiconductor device assembly of claim 18, further comprising a second intermediate substrate including a fifth set of castellated connectors on at least one peripheral edge thereof, said fifth set of castellated connectors having substantially the same pitch as corresponding castellated connectors of said second set, corresponding castellated connectors of said second and fifth sets in communication with one another.

24. The semiconductor device assembly of claim 18, further comprising:

a support substrate including conductive connection sites on a surface thereof having substantially the same pitch as that of said first set of castellated connectors and in electrical communication with corresponding castellated connectors of said first set; and

module connectors in electrical communication with corresponding conductive connection sites of said support substrate, said module connectors being configured to establish electrical communication between semiconductor devices of the semiconductor device assembly and other external devices by way of a circuit board.

25. The semiconductor device assembly of claim 18, comprising a low-profile electronic system.

26. A semiconductor device assembly, comprising:

a first semiconductor device component comprising a plurality of first connectors positioned on a peripheral edge thereof, each of said first connectors including a recess that extends substantially from a first major surface of said first semiconductor device component to an opposite, second major surface of said first semiconductor device component; and

a second semiconductor device component comprising a plurality of second connectors positioned on a peripheral edge thereof, each of said second connectors including a recess that extends substantially from a first major surface of said second semiconductor device component to an opposite, second major surface of said second semiconductor device component, corresponding ones of said first and second connectors being alignable with one another upon placement of said first and second semiconductor device components in an assembled relationship.

27. The semiconductor device assembly of claim 26, wherein at least one of said first and second semiconductor device components comprises a semiconductor device.

28. The semiconductor device assembly of claim 26, wherein at least one of said first and second semiconductor device components comprises at least one of an interposer, an intermediate substrate, and a carrier substrate.

29. The semiconductor device assembly of claim 26, wherein at least one of said first and second semiconductor device components comprises exposed contact pads on a major surface thereof.

30. The semiconductor device assembly of claim 26, wherein said recess comprises a semicylindrical recess with ends thereof being located adjacent to opposite major surfaces of said first or second semiconductor device component.

31. The semiconductor device assembly of claim 26, further comprising a plurality of conductive elements positioned to establish electrical communication between corresponding ones of said first and second connectors.

32. The semiconductor device assembly of claim 31, wherein said plurality of conductive elements at least partially secures said first and second semiconductor device components to one another.

33. The semiconductor device assembly of claim 26, wherein each said recess is configured to at least partially receive an elongate conductive structure and to establish electrical contact between a corresponding connector and said elongate conductive structure.

34. The semiconductor device assembly of claim 26, wherein at least some of said second connectors are located so as not to correspond to a position of any of said first connectors upon placement of said first and second semiconductor device components in said assembled relationship.

35. A method for assembling semiconductor device components, comprising:

providing a first semiconductor device component including a plurality of contact areas;

providing a second semiconductor device component comprising a plurality of conductive connectors positioned on at least one peripheral edge thereof;

aligning at least some conductive connectors of said plurality of conductive connectors with corresponding contact areas of said plurality of contact areas; and

electrically connecting said at least some conductive connectors with said corresponding contact areas.

36. The method of claim 35, wherein said providing said first semiconductor device component comprises providing at least one of an intermediate substrate, a support substrate, a circuit board, and a semiconductor device.

37. The method of claim 36, wherein said providing said second semiconductor device component comprises providing at least one semiconductor device.

38. The method of claim 35, wherein said providing said first semiconductor device component comprises providing a first semiconductor device component with at least some contact areas of said plurality of contact areas being located on a peripheral edge of said first semiconductor device component.

39. The method of claim 35, wherein said providing said second semiconductor device component comprises providing a second semiconductor device component with at least some conductive connectors of said plurality of conductive connectors including recesses formed therein and extending substantially from a first major surface of said second semiconductor device component to an opposite, second major surface of said second semiconductor device component.

40. The method of claim 39, wherein said providing said second semiconductor device comprises providing said second semiconductor device component with said recesses of said at least some conductive connectors comprising semicylindrical recesses.

41. The method of claim 35, wherein said electrically connecting comprises placing conductive material between said at least some conductive connectors and said corresponding contact areas.

42. The method of claim 41, wherein said electrically connecting further comprises bonding discrete quantities of said conductive material to each conductive connector of said at least some conductive connectors and a corresponding contact area of said corresponding contact areas.

43. The method of claim 41, wherein said placing conductive material comprises placing solder between said at least some conductive connectors and said corresponding contact areas.