Semiconductor device and manufacturing method thereof

• US 20030230805A1
• Filed: 04/23/2003
• Published: 12/18/2003
• Est. Priority Date: 04/23/2002
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Noma, Takashi, Tokushige, Ryoji, Takai, Nobuyuki, Kitagawa, Katsuhiko, Shinogi, Hiroyuki, Okigawa, Mitsuru, Otagaki, Takayasu, Ando, Tatsuya
• Granted Patent: US 7,312,521 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.

Claims

1. A semiconductor device comprising:

a semiconductor die;

a first insulation film disposed on a top surface of the semiconductor die;

a first wiring portion disposed on the first insulation film;

a holding substrate disposed over the top surface of the semiconductor die and holding the semiconductor die;

a second insulation film comprising a side film and a back film, the side film being disposed on a side surface of the semiconductor die and the back film being disposed on a back surface of the semiconductor die;

a second wiring portion disposed on the side film and the back film and connected to the first wiring portion; and

a conductive terminal formed on the second wiring.

2. The semiconductor device of claim 1, wherein the second wiring portion is connected to a side surface of the first wiring portion, the side surface of the first wiring portion being aligned along the thickness direction of the first wiring portion.

3. The semiconductor device of claim 1, wherein the second wiring portion is connected to a back surface of the first wiring portion, the back surface of the first wiring portion facing the first insulation film.

4. The semiconductor device of claim 3, wherein a length of a contacting portion between the second wiring portion and the back surface of the first wiring portion is longer than a thickness of the first wiring portion.

5. The semiconductor device of claim 1, wherein the second wiring portion is connected to a back surface of the first wiring portion and a side surface of the first wiring portion, the side surface of the first wiring portion being aligned along the thickness direction of the first wiring portion and the back surface of the first wiring portion facing the first insulation film.

6. The semiconductor device of claim 5, wherein a length of a contacting portion between the second wiring portion and the back surface of the first wiring portion is longer than a thickness of the first wiring portion.

7. The semiconductor device of claim 1, further comprising a cushion disposed between the second wiring portion and the second insulation film.

8. The semiconductor device of claim 1, wherein the holding substrate is a glass plate, a plastic plate, a film, a silicon substrate, a reclaimed silicon substrate, an oxide film or a transparent resin plate.

9. A manufacturing method of a semiconductor device comprising:

providing a semiconductor wafer having a first die and a second die, a top surface of the wafer being covered by a first insulation film;

forming a first wiring portion on the first insulation film so that the first wiring portion is disposed above the first and second dice;

bonding a holding substrate to the wafer so that the holding substrate faces the top surface of the wafer;

etching a back surface of the wafer along a border between the first and second dice to expose a part of the first wiring portion and to expose a side surface and a back surface of the first die and a side surface and a back surface of the second die;

forming a second insulation film on the exposed side surfaces and top surfaces of the first and second dice;

etching the first wiring portion to cut the first wiring portion in two;

forming a second wiring portion on the second insulation film so that the second wiring portion is connected to one of the cut first wiring portions and extends to the back surface of the corresponding die;

forming a conductive terminal on the second wiring portion; and

separating the first and second dice.

10. The manufacturing method of a semiconductor device of claim 9, wherein the forming of the second wiring portion comprises exposing a cut surface of said one of the cut wiring portions and connecting the second wiring portion to the cut surface.

11. The manufacturing method of a semiconductor device of claim 9, wherein the forming of the second wiring portion comprises exposing a back surface of said one of the cut wiring portions and connecting the second wiring portion to the back surface.

12. The manufacturing method of a semiconductor device of claim 9, wherein the forming of the second wiring portion comprises exposing a cut surface and a back surface of said one of the cut wiring portions and connecting the second wiring portion to the cut surface and the back surface.

13. The manufacturing method of a semiconductor device of claim 9, wherein the holding substrate is a glass plate, a plastic plate, a film, a silicon substrate, a reclaimed silicon substrate, an oxide film or a transparent resin plate.

14. A manufacturing method of a semiconductor device comprising:

providing a semiconductor wafer having a first die and a second die, a top surface of the wafer being covered by a first insulation film;

forming a first top wiring portion and a second top wiring portion on the first insulation film so that the first and second top wiring portions are disposed above the first and second dice, respectively;

bonding a holding substrate to the wafer so that the holding substrate faces the top surface of the wafer;

etching a back surface of the wafer along a border between the first and second dice to expose a part of the first top wiring portion and a part of the second top wiring portion and to expose a side surface and a back surface of the first die and a side surface and a back surface of the second die;

forming a second insulation film on the exposed side surfaces and top surfaces of the first and second dice;

forming a first bottom wiring portion on the second insulation film so that the first bottom wiring portion is connected to the first top wiring portion and extends to the back surface of the first die;

forming a second bottom wiring portion on the second insulation film so that the second bottom wiring portion is connected to the second top wiring portion and extends to the back surface of the second die;

forming a first conductive terminal on the first bottom wiring portion and forming a second conductive terminal on the second bottom wiring portion; and

separating the first and second dice.

15. The manufacturing method of a semiconductor device of claim 14, wherein the forming of the first and second bottom wiring portions comprises exposing a back surface of each of the first and second top wiring portions and connecting the first and second bottom wiring portions to the corresponding exposed back surfaces.

16. The manufacturing method of a semiconductor device of claim 14, wherein the forming of the first and second bottom wiring portions comprises exposing a back surface and a side surface of each of the first and second top wiring portions and connecting the first and second bottom wiring portions to the corresponding exposed back and side surfaces.

17. The manufacturing method of a semiconductor device of claim 14, wherein the holding substrate is a glass plate, a plastic plate, a film, a silicon substrate, a reclaimed silicon substrate, an oxide film or a transparent resin plate.

18. A semiconductor device comprising:

a semiconductor die;

a first insulation film disposed on a top surface of the semiconductor die;

a first wiring portion disposed on the first insulation film;

a holding substrate disposed over the top surface of the semiconductor die and holding the semiconductor die;

a second insulation film disposed on a side surface and a back surface of the semiconductor die;

a second wiring portion disposed on the second insulating and connected to a back surface of the first wiring portion, the back surface facing the top surface of the semiconductor die; and

a conductive terminal formed on the second wiring.