Sequential DC offset correction for amplifier chain

• US 20030231054A1
• Filed: 06/13/2002
• Published: 12/18/2003
• Est. Priority Date: 06/13/2002
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Molnar, Alyosha C., Magoon, Rahul
• Granted Patent: US 6,753,727 B2
• Time in Patent Office: Days
• US Class Current: 330/9
• CPC Class Codes: H03F 3/45977 using switching means, e.g. sample and hold

Abstract

An amplifier chain with sequential DC offset correction for use in a radio receiver is provided. The amplifier chain has at least first and second amplifier stages connected in series. The first and second stages include an amplifier and a track and hold circuit connected in parallel across the amplifier. The track and hold circuit has a tracking state and a holding state. A control signal is coupled to the track and hold circuits of the first and second stages. The control signal is configured to set the track and hold circuits to the tracking state, which may be done simultaneously, and to sequentially set the track and hold circuit of the first stage to the holding state and then set the track and hold circuit of the second stage to the holding state.

Claims

1. An amplifier chain comprising:

a) a first amplifier,

b) a first track and hold circuit, coupled to the first amplifier and having a tracking state and a holding state;

c) a second amplifier, coupled to the first amplifier;

d) a second track and hold circuit, coupled to the second amplifier and having a tracking state and a holding state; and

e) a control circuit which generates a control signal, coupled to the first track and hold circuit and to the second track and hold circuit, the control signal configured to set the first track and hold circuit to the tracking state and to set the second track and hold circuit to the tracking state, and to sequentially set the first track and hold circuit to the holding state and then set the second track and hold circuit to the holding state.

2. The amplifier chain of claim 1, wherein the control signal sets first and second track and hold circuits to the tracking state substantially simultaneously.

3. The amplifier chain of claim 1, wherein the first and second track and hold circuits comprise:

a) a holding capacitor,

b) a tracking amplifier selectively coupled to the holding capacitor when the track and hold circuit is in the tracking state; and

c) a buffer having a buffer input coupled to the holding capacitor and a buffer output selectively coupled to an input of an amplifier of the amplifier chain when the track and hold circuit is in the holding state.

4. The amplifier chain of claim 1, wherein the first and second track and hold circuits comprise:

a) a comparator, having a first input connected to a DC offset current from an amplifier, of the amplifier chain, a second input, connected to a reference signal, and an output;

b) a counter, having an input coupled to the output of the comparator and an output;

c) a current mode digital to analog converter, having an input connected to the output of the counter and an output connected to the first input of the comparator; and

d) data register connected to the output of the counter.

5. The amplifier chain of claim 1 further comprising:

a) a first low pass filter having a narrow bandwidth state and a high bandwidth state coupled in series with the first amplifier output and the second amplifier input; and

b) a high bandwidth control signal, coupled to the first low pass filter.

6. The amplifier chain of claim 1, further comprising:

a) a third amplifier, coupled to the second amplifier; and

b) a third track and hold circuit, coupled to the third amplifier and having a tracking state and a holding state;

wherein the control signal is further coupled to the third track and hold circuit, the control signal further configured to set the first, second, and third track and hold circuits to their respective tracking states, and further to sequentially set the first track and hold circuit to its holding state, set the second track and hold circuit to its holding state; and

set the third track and hold circuit to its holding state.

7. The amplifier chain of claim 6 further comprising:

a) a first low pass filter having a narrow bandwidth state and a high bandwidth state coupled in series with the first amplifier and the second amplifier.

b) a second low pass filter having a narrow bandwidth state and a high bandwidth state coupled in series with the second amplifier and the third amplifier input; and

c) a high bandwidth control signal, coupled to the first low pass filter and coupled to the second low pass filter.

8. An amplifier for use in a radio receiver having a mixer, which generates an in-phase mixer output and a quadrature phase mixer output, the amplifier comprising:

a) an in-phase amplifier chain, coupled to the in-phase mixer output, the in phase amplifier chain including;

1) a first amplifier coupled to a first track and hold circuit;

2) a second amplifier coupled in series with the first amplifier, the second amplifier coupled to a second track and hold circuit; and

b) a quadrature phase amplifier chain, coupled to the quadrature phase mixer output, the quadrature phase amplifier chain including;

1) a third amplifier coupled to a third track and hold circuit;

2) a fourth amplifier coupled in series with the third amplifier and coupled to a fourth track and hold circuit; and

c) a control circuit which generates a control signal coupled to the first, second, third and fourth track and hold circuits, the control signal configured to set the first, second, third and fourth track and hold circuits to a tracking state, and configured to sequentially set the first track and hold circuit, to a holding state and set the second track and hold circuit to a holding state, and to sequentially set the third track and hold circuit to a holding state and set the fourth track and hold circuit to a holding state.

9. The amplifier of claim 8 further comprising:

a) a first low pass filter having a narrow bandwidth state and a high bandwidth state coupled in series with the first amplifier and the second amplifier;

b) a second low pass filter having a narrow bandwidth state and a high bandwidth state coupled in series with the third amplifier and the fourth amplifier; and

c) a high bandwidth control signal, coupled to the first and second low pass filters.

10. An amplifier chain comprising:

a) first means for amplifying;

b) first means for correcting DC offset coupled to the first means for amplifying, the first means for correcting DC offset further having a tracking state and a holding state;

c) a second means for amplifying, coupled to the first means for amplifying;

d) a second means for correcting DC offset coupled to the second means for amplifying the second means for correcting DC offset having a tracking state and a holding state; and

e) means for controlling the states of the first means for correcting DC offset and the second means for correcting DC offset, the means for controlling further comprising a means for setting the first means for correcting DC offset to the tracking state, for setting the second means for correcting DC offset to the tracking state, and for sequentially setting the first means for correcting DC offset to the holding state and setting the second means for correcting DC offset to the holding state.

11. The amplifier chain of claim 10, wherein the means for controlling further comprises means for setting the first means for correcting DC offset and the second means for correcting DC offset to the tracking state substantially simultaneously.

12. The amplifier chain of claim 10, wherein each for correcting DC offset comprises:

a) means for holding a DC offset voltage of a means for amplifying,

b) means for tracking the DC offset voltage and for selectively applying the DC offset voltage to the means for holding; and

c) means for selectively applying the DC offset voltage to an input of the means for amplifying.

13. The amplifier chain of claim 10, wherein each means for correcting DC offset comprises:

a) means for generating a DC offset correction current based on a digital input signal;

b) means for comparing a sum of a DC offset current from a means for amplifying and the DC offset correction current with a reference;

c) means for incrementing the digital input signal when the means for comparing detects that the DC offset current from an amplifier is not corrected by the DC offset correction current, the means for incrementing the digital input signal connected to the means for generating a DC offset correction current; and

d) means for storing the digital input signal when the means for comparing detects that the DC offset current from a means for amplifying is corrected by the DC offset correction current, the means for storing connected to the means for incrementing the digital input signal.

14. The amplifier chain of claim 10 further comprising:

a) first means for filtering having a narrow bandwidth state and a high bandwidth state coupled in series with the first means for amplifying and the second means for amplifying; and

b) means for controlling the bandwidth of the first means for filtering.

15. The amplifier chain of claim 10, further comprising:

a) third means for amplifying, coupled to the second means for amplifying; and

b) third means for correcting DC offset coupled to the third means for amplifying, the third means for correcting DC offset having a tracking state and a holding state;

wherein the means for controlling further comprises means for controlling the state of the third means for correcting DC offset, the means for controlling further comprising a means for setting the third means for correcting DC offset to the tracking state and for sequentially setting the first means for correcting DC offset to the holding state, setting the second means for correcting DC offset to the holding state, and setting the third means for correcting DC offset to the holding state.

16. The amplifier chain of claim 15 further comprising:

a) first means for filtering having a narrow bandwidth state and a high bandwidth state coupled in series with the first means for amplifying and the second means for amplifying;

b) second means for filtering having a narrow bandwidth state and a high bandwidth state coupled in series with the second means for amplifying and the third means for amplifying; and

c) means for controlling the bandwidth of the first and second means for filtering.

17. A method for correcting DC offset in an amplifier chain having at least first and second amplifiers coupled in series, each amplifier being coupled to a track and hold circuit having a tracking state and a holding state, comprising:

a) setting a first track and hold circuit to the tracking state;

b) setting a second track and hold circuit to the tracking state;

c) setting the first track and hold circuit to the holding state; and

d) setting the second track and hold circuit to the holding state after setting the first track and hold circuit to the holding state;

wherein the second track and hold circuit is subsequent to the first track and hold circuit in the amplifier chain.

18. The method as recited in claim 17, wherein the steps of setting the first track and hold circuit to the tracking state occurs substantially simultaneously with the step of setting the second track and hold circuit to the tracking state.

19. The method as recited in claim 17, wherein the amplifier chain includes at least one filter having a narrow bandwidth state and a high bandwidth state the filter coupled in series with an amplifier, further comprising the steps of:

a) setting the filter to the high bandwidth state while the track and hold circuits are in the tracking state; and

b) setting the filter to the narrow bandwidth state when the track and hold circuits are in the holding state.

20. A method for correcting DC offset in a radio circuit prior to a time slot in a time division multiplex format, the radio circuit having at least first and second amplifier stages, the method comprising:

a) turning on at least a portion or the radio circuit at a first time prior to the timeslot;

b) activating tracking of the DC offset in at least the first and second amplifier stages after the first time and before the timeslot;

c) activating a holding state to hold the DC offset of at least the first and second amplifier stages at a time after tracking is activated and before the timeslot;

d) enabling the radio frequency amplifier at a time before the timeslot, but occurring after activating the holding state.

21. The method as recited in claim 20, wherein at least one amplifier stage has a filter having a narrow bandwidth state and a high bandwidth state, further comprising the steps of:

a) setting the filter to the high bandwidth state at a time prior to the timeslot, but occurring no later than the time of activating tracking; and

b) setting the filter to the narrow bandwidth state at a time prior to the timeslot, and occurring no earlier than the time the holding state is activated.

22. The method of claim 20 wherein the step of activating tracking comprises comparing the DC offset of at least the first and second amplifier stages to a reference.