Non-volatile differential dynamic random access memory

• US 20030231528A1
• Filed: 03/19/2003
• Published: 12/18/2003
• Est. Priority Date: 03/19/2002
• Status: Active Grant

• Current Assignee: O2ic, Inc.
• Original Assignee: 021C Incorporated
• Inventors: Choi, Kyu Hyun, Li, Sheau-suey
• Granted Patent: US 6,954,377 B2
• Time in Patent Office: Days
• US Class Current: 365/199
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Abstract

In accordance with the present invention, a memory cell includes a pair of non-volatile devices and a pair of DRAM cells each associated with a different one of the non-volatile devices. Each DRAM cell further includes an MOS transistor a capacitor. The DRAM cells and their associated non-volatile devices operate differentially and when programmed store and supply complementary data. The non-volatile devices are erased prior to being programmed. Programming of the non-volatile devices may be done via hot-electron injection or Fowler-Nordheim tunneling. When a power failure occurs, the data stored in the DRAM are loaded in the non-volatile devices. After the power is restored, the data stored in the non-volatile devices are restored in the DRAM cells. The differential reading and wring of data reduces over-erase of the non-volatile devices.

Claims

1. A memory cell comprising:

a first MOS transistor having a first current carrying terminal coupled to a first node, a second current carrying terminal coupled to a first bitline associated with the memory cell, and a gate terminal coupled to a first terminal of the memory cell; and

a first non-volatile device associated with the first MOS transistor and comprising;

a first substrate region coupled to a second terminal of the memory;

a source region formed in the first substrate region and coupled to the first node;

a drain region formed in the first substrate region and separated from the source region by a first channel region;

said drain region being coupled to a third terminal of the memory cell;

a first gate overlaying a first portion of the first channel region and separated therefrom via a first insulating layer;

said first gate coupled to a fourth terminal of the memory cell; and

a second gate overlaying a second portion of the first channel region and separated therefrom via a second insulating layer;

wherein said first portion of the first channel region and said second portion of the channel do not overlap and wherein said second gate is coupled to a fifth terminal of the memory cell,

a second MOS transistor having a first current carrying terminal coupled to the second node, a second current carrying terminal coupled to a second bitline associated with the memory cell, and a gate terminal coupled to the first terminal of the memory cell; and

a second non-volatile device associated with the second MOS transistor and comprising;

a second substrate region coupled to the second terminal of the memory;

a source region formed in the second substrate region and coupled to the second node;

a drain region formed in the second substrate region and separated from the source region of the second substrate region by a second channel region;

said drain region of the second substrate region being coupled to the third terminal of the memory cell;

a first gate overlaying a first portion of the second channel region and separated therefrom via a first insulating layer and coupled to the fourth terminal of the memory cell; and

a second gate overlaying a second portion of the second channel region and separated therefrom via a second insulating layer;

wherein said first portion of the second channel region and said second portion of the second channel region do not overlap and wherein said second gate overlaying the second portion of the second channel region is coupled to the fifth terminal of the memory cell.

2. The memory cell of claim 1 wherein each of said first and second nodes have active capacitors formed thereon.

3. The memory cell of claim 2 wherein the first and second nodes receive their respective voltages from the first and second bitlines and maintain their respective voltages after the first and third MOS transistors are turned off.

4. The memory cell of claim 3 wherein the first and second non-volatile devices are adapted to store charges representative of the voltages of the first and second nodes during a power-off cycle.

5. The memory cell of claim 4 wherein during the power-off cycle, the second terminal of the memory cell is adapted to receive the first voltage, the third terminal of the memory cell is adapted to receive a second voltage, the fourth terminal of the memory cell is adapted to receive a third supply voltage, and the fifth terminal of the memory cell is adapted to receive a fourth supply voltage.

6. The memory cell of claim 5 wherein the fourth voltage is greater than the first, second and third voltages.

7. The memory cell of claim 6 wherein the first voltage is 0 volt.

8. The memory cell of claim 6 wherein during the power-off cycle one of the first and second non-volatile devices traps more electrons in its nitride layer than does the other one of the first and second non-volatile devices

9. The memory cell of claim 8 wherein the electrons are trapped via hot-electron injection.

10. The memory cell of claim 8 wherein after the power-off cycle, the first and second nodes store charges they had prior to the power-off cycle.

11. The memory cell of claim 10 wherein after the power-off cycle, the first voltage is applied to the first and second terminals, the second voltage is applied to the third and fifth input terminals, and a fifth voltage is applied to the fourth terminal, wherein the fifth voltage is smaller than the second voltage.

12. The memory cell of claim 11 wherein the trapped electrons are untrapped by applying the first voltage to first, second and third terminals of the memory cell, applying a negative voltage to the fifth terminal of the memory cell and by enabling the fourth terminal of the memory cell to float.

13. The memory cell of claim 12 wherein said first and second MOS transistors are periodically turned on.