Transaction management in systems having multiple multi-processor clusters

• US 20030233388A1
• Filed: 05/28/2002
• Published: 12/18/2003
• Est. Priority Date: 05/28/2002
• Status: Active Grant

• Current Assignee: Sanmina-SCI Corporation
• Original Assignee: Newisys, Inc. (Sanmina-SCI Corporation)
• Inventors: Oehler, Richard R., Glasco, David Brian, Kota, Rajesh, Prasadh, Guru, Zeitler, Carl
• Granted Patent: US 7,155,525 B2
• Time in Patent Office: Days
• US Class Current: 718/101
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus

Abstract

A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.

Claims

1. A computer system comprising a plurality of processor clusters, each cluster including a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture, each cluster having a local transaction space associated therewith for uniquely identifying locally generated transactions within the cluster, wherein the interconnection controller in each cluster is operable to uniquely map selected ones of locally generated transactions directed to others of the clusters to a global transaction space, and remotely generated transactions directed to the local nodes to the local transaction space.

2. The computer system of claim 1 wherein each of the locally generated transactions is identified by a local transaction tag within the local transaction space, the interconnection controller being operable to generate a global transaction tag and associate the global transaction tag with the local transaction tag.

3. The computer system of claim 2 wherein the interconnection controller is operable to associate the global and local transaction tags by temporarily storing both in an associated buffer.

4. The computer system of claim 2 wherein the interconnection controller is associated with a corresponding node in the point-to-point architecture.

5. The computer system of claim 4 wherein the local transaction tag comprises a node ID identifying one of the corresponding and local nodes from which the corresponding locally generated transaction originated.

6. The computer system of claim 5 wherein selected ones of the local nodes comprise various combinations of corresponding units including any of at least one central processing unit, at least one memory controller, and at least one input/output interface, the local transaction tag further comprising a unit ID identifying one of the units.

7. The computer system of claim 6 wherein the local transaction tag further comprises a locally unique transaction ID.

8. The computer system of claim 7 wherein node ID comprises 3 bits, the unit ID comprises 2 bits and the locally unique transaction ID comprises 5 bits.

9. The computer system of claim 2 wherein the global transaction tag comprises a globally unique transaction ID and a cluster ID identifying a first one of the clusters from which an associated transaction originated.

10. The computer system of claim 9 wherein the globally unique transaction ID comprises T bits and the cluster ID comprises Q bits, Q being related to a number of clusters and T being related to the number of clusters and a size of the local transaction space.

11. The computer system of claim 10 wherein T is greater than or equal to 7 and Q is greater than or equal to 2.

12. The computer system of claim 1 wherein the plurality of clusters comprises four clusters.

13. The computer system of claim 12 wherein the plurality of local nodes in each cluster comprises four local processors.

14. The computer system of claim 1 wherein the interconnection controller in each cluster is further operable to map locally generated address information to others of the clusters, and remotely generated address information to the local nodes.

15. The computer system of claim 1 wherein the point-to-point architecture comprises a plurality of local point-to-point links and wherein the plurality of clusters are interconnected with a plurality of global links, the interconnection controller in each cluster further being operable using global routing information to map locally generated transmissions directed to others of the clusters to the global links, and using local routing information to map remotely generated transmissions directed to the local nodes to the local links.

16. The computer system of claim 15 wherein the global links are point-to-point links.

17. The computer system of claim 15 wherein the global links are not point-to-point links.

18. The computer system of claim 1 wherein the point-to-point architecture comprises a plurality of local point-to-point links and wherein the plurality of clusters are interconnected with a plurality of global links, the interconnection controller in each cluster further being operable using global routing information to map locally generated transmissions directed to others of the clusters to the global links, and using local routing information to map remotely generated transmissions directed to the local nodes to the local links, and wherein the interconnection controller in each cluster is further operable to map locally generated address information to the other clusters, and remotely generated address information to the local nodes.

19. The computer system of claim 18 wherein the global links are point-to-point links.

20. The computer system of claim 18 wherein the global links are not point-to-point links.

21. In a computer system comprising a plurality of processor clusters, each cluster including a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture, a method for managing transactions in a global transaction space associated with the plurality of clusters, the method comprising:

defining a local transaction space for each cluster in which locally generated transactions are uniquely identified within the cluster;

uniquely mapping selected ones of the locally generated transactions directed to others of the clusters to the global transaction space; and

mapping remotely generated transactions directed to the local nodes to the local transaction space.

22. An interconnection controller for use in a computer system having a plurality of processor clusters, each cluster including a plurality of local nodes and an instance of the interconnection controller interconnected by a local point-to-point architecture, each cluster having a local transaction space associated therewith for uniquely identifying locally generated transactions within the cluster, interconnection controller comprising circuitry which is operable to uniquely map selected ones of locally generated transactions directed to others of the clusters to a global transaction space, and remotely generated transactions directed to the local nodes to the local transaction space.

23. An integrated circuit comprising the interconnection controller of claim 22.

24. The integrated circuit of claim 23 wherein the integrated circuit comprises an application-specific integrated circuit.

25. At least one computer-readable medium having data structures stored therein representative of the interconnection controller of claim 22.

26. The at least one computer-readable medium of claim 25 wherein the data structures comprise a simulatable representation of the interconnection controller.

27. The at least one computer-readable medium of claim 26 wherein the simulatable representation comprises a netlist.

28. The at least one computer-readable medium of claim 25 wherein the data structures comprise a code description of the interconnection controller.

29. The at least one computer-readable medium of claim 28 wherein the code description corresponds to a hardware description language.

30. A set of semiconductor processing masks representative of at least a portion of the interconnection controller of claim 22.