Addressing scheme supporting fixed local addressing and variable global addressing

• US 20030233495A1
• Filed: 05/15/2003
• Published: 12/18/2003
• Est. Priority Date: 05/15/2002
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rowlands, Joseph B., Moll, Laurent R.
• Granted Patent: US 7,340,546 B2
• Time in Patent Office: Days
• US Class Current: 710/1
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/082 Associative directories G06F12/0822 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions

Abstract

A node comprises one or more resources and a register programmable with an indication during use. The one or more resources are addressed with addresses within a local region of an address space. The indication identifies a second region of the address space that is aliased to the local region, and other nodes address the one or more resources using addresses in the second region.

Claims

1. A node comprising:

one or more resources; and

a register programmable with an indication during use;

wherein the one or more resources are addressed with addresses within a local region of an address space, and wherein the indication identifies a second region of the address space that is aliased to the local region, wherein other nodes address the one or more resources using addresses in the second region.

2. The node as recited in claim 1 wherein the indication comprises a set of most significant bits of the addresses included in the second region, and wherein the remainder of each address in the second region identifies one of the resources within the second region.

3. The node as recited in claim 1 wherein the indication comprises a set of bits of the addresses included in the second region, and wherein the remainder of each address in the second region identifies one of the resources within the second region.

4. The node as recited in claim 1 wherein internode coherency is maintained for transactions that use addresses in the second region.

5. The node as recited in claim 4 wherein internode coherency is not maintained for transactions that use addresses in the local region.

6. The node as recited in claim 4 further comprising an agent, the agent initiating a transaction to access one of the resources using an address in the second region to perform the transaction with internode coherency maintained.

7. The node as recited in claim 1 wherein the one or more resources comprise memory coupled to the node.

8. The node as recited in claim 1 wherein the one or more resources comprise local I/O devices or interfaces in the node.

9. The node as recited in claim 1 wherein intranode coherency is not maintained between a first address in the local region that addresses a first resource and a second address in the second region that addresses the first resource.

10. A system comprising:

a first node comprising one or more first resources and a first register programmable with a first indication during use; and

a second node comprising one or more second resources and a second register programmable with a second indication during use, the second indication different than the first indication during use;

wherein the first resources are addressable within the first node using addresses within a local region of a first address space implemented by the first node, and wherein the second resources are addressable within the second node using addresses within the local region of a second address space implemented by the second node, and wherein the first indication identifies a second region of the first address space that is aliased to the local region in the first node, and wherein the first resources are addressable by the second node using the second region, and wherein the second indication identifies a third region of the second address space that is aliased to the local region in the second node, and wherein the second resources are addressable by the first node using the third region.

11. The system as recited in claim 10 wherein the first indication and the second indication each comprise a set of most significant bits of the addresses included in the second region and the third region, respectively, and wherein the remainder of each address in the second region identifies one of the resources within the second region, and wherein the remainder of each address in the third region identifies one of the resources within the third region.

12. The system as recited in claim 10 wherein internode coherency is maintained for transactions that use addresses in the second region and the third region.

13. The system as recited in claim 12 wherein internode coherency is not maintained for transactions that use addresses in the local region.

14. The system as recited in claim 13 wherein the first node further comprises an agent, the agent initiating a first transaction, during use, to access one of the first resources using a first address in the second region to perform the first transaction with internode coherency maintained.

15. The system as recited in claim 14 wherein the agent initiates a second transaction, during use, to access one of the first resources using a second address in the local region to perform the second transaction without maintaining internode coherency.

16. The system as recited in claim 10 wherein the one or more first resources comprise memory coupled to the first node.

17. The system as recited in claim 10 wherein the one or more first resources comprise local I/O devices or interfaces in the first node.

18. A method comprising:

selecting one of a first address or a second address to address a first resource in a first node, the first address being in a local region of an address space and the second address being in a second region of the address space that is aliased to the local region in the first node; and

using the one of the first address or the second address as the address of the transaction.

19. The method as recited in claim 18 wherein the selecting comprises:

determining if internode coherency is desired for the first resource; and

selecting the second address if internode coherency is desired.

20. The method as recited in claim 19 further comprising selecting the first address if internode coherency is not desired.

21. The method as recited in claim 18 wherein the selecting comprises:

determining if shared access by other nodes is desired for the first resource; and

selecting the second address if shared access is desired.

22. The method as recited in claim 21 further comprising selecting the first address if shared access is not desired.