Round-robin updating for high speed i/o parallel interfaces

• US 20030233608A1
• Filed: 06/18/2002
• Published: 12/18/2003
• Est. Priority Date: 06/18/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Amick, Brian W., Roy, Aninda K., Gauthier, Claude R.
• Granted Patent: US 7,017,086 B2
• Time in Patent Office: Days
• US Class Current: 714/744
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922

Abstract

A technique for adjusting a communication system involves a plurality of links where each link includes a data line adapted to transmit a data signal and a clock line adapted to transmit a clock signal. A test circuit connects to the plurality of links where the test circuit tests at least one of the plurality of links. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal of the one of the plurality of links based on an offset where the adjustment circuit adjusts a timing of the adjustable clock signal relative to the data signal of the one of the plurality of links. The test circuit is adapted to perform a round-robin testing of the plurality of the links.

Claims

1. A communication system, comprising:

a plurality of links wherein each link comprises a data line adapted to transmit a data signal and a clock line adapted to transmit a clock signal;

a first latch device arranged to latch a signal on the data line of at least one of the plurality of links; and

a first test circuit operatively connected to the plurality of links, wherein the first test circuit tests at least the one of the plurality of links, the first test circuit comprising;

a first adjustment circuit arranged to generate a first adjustable clock signal from the clock signal of the one of the plurality of links being tested, wherein the first adjustment circuit adjusts a timing of the first adjustable clock signal relative to the data signal of the one of the plurality of links being tested, wherein the first latch device is responsive to the first adjustable clock signal, and

a first pattern comparator arranged to compare a first latched test pattern signal to a first test pattern signal, wherein the first latched test pattern signal comprises the first test pattern signal latched from the data line of the one of the plurality of links by the first latch device,

wherein the first test circuit is adapted to perform a round-robin testing of the plurality of the links.

2. The communication system of claim 1, further comprising:

a second latch device arranged to latch a signal on the data line of at least another one of the plurality of links; and

a second test circuit operatively connected to the plurality of links, wherein the second test circuit tests at least the another one of the plurality of links, the second test circuit comprising;

a second adjustment circuit arranged to generate a second adjustable clock signal from the clock signal of the another one of the plurality of links being tested, wherein the second adjustment circuit adjusts a timing of the second adjustable clock signal relative to the data signal of the another one of the plurality of links being tested, wherein the second latch device is responsive to the second adjustable clock signal, and

a second pattern comparator arranged to compare a second latched test pattern signal to a second test pattern signal, wherein the second latched test pattern signal comprises the second test pattern signal latched from the data line of the another one of the plurality of links by the second latch device,

wherein the second test circuit is adapted to perform a round-robin testing of the plurality of the links.

3. The communication system of claim 2, wherein the first test pattern and the second test pattern are identical.

4. The communication system of claim 2, wherein

the first test circuit is connected to at least a first link of the plurality of links,

the second test circuit is connected to at least a second link of the plurality of links, and

the first test circuit is connected to the second test circuit.

5. The communication system of claim 1, wherein the first test circuit is arranged to cause the first test pattern signal to be transmitted on at least one of the plurality of links.

6. The communication system of claim 1, wherein the first test circuit tests at least one of the plurality of links while another of the plurality of links transmits a non-test pattern signal.

7. The communication system of claim 1, wherein the first test circuit tests at least one of the plurality of links based on a counter.

8. The communication system of claim 1, wherein the first test circuit tests at least one of the plurality of links when the at least one of the plurality of links is idle.

9. The communication system of claim 1, wherein the first test circuit tests at least one of the plurality of links when a CPU stall occurs.

10. The communication system of claim 1, wherein the first test circuit tests at least one of the plurality of links periodically.

11. The communication system of claim 1, wherein at least one of the plurality of links is available to be tested at all times.

12. The communication system of claim 1, wherein the first adjustable clock signal is generated from a voltage controlled delay line.

13. The communication system of claim 1, wherein the first adjustable clock signal is generated from a digital delay line.

14. The communication system of claim 1, wherein the first adjustable clock signal is generated from an analog delay line.

15. A communication system updating method, comprising:

testing a first adjustable clock signal for one of a plurality of links, comprising;

transmitting a first test pattern signal on a data line of the one of the plurality of links,

latching the first test pattern signal based on the first adjustable clock signal to generate a first latched test pattern signal,

comparing the first latched test pattern signal to the first test pattern signal,

adjusting a first offset of the first adjustable clock based on the comparing of the first latched test pattern signal to the first test pattern signal; and

round-robin testing each of the plurality of links.

16. The method of claim 15, further comprising:

testing a second adjustable clock signal for another one of the plurality of links, comprising;

transmitting a second test pattern signal on a data line of the another one of the plurality of links,

latching the second test pattern signal based on the second adjustable clock signal to generate a second latched test pattern signal, comparing the second latched test pattern signal to the second test pattern signal, and

adjusting a second offset of the second adjustable clock based on the comparing of the second latched test pattern signal to the second test pattern signal.

17. The method of claim 16, wherein the testing the first adjustable clock signal and testing the second adjustable clock signal do not occur at the same time.

18. The method of claim 15, wherein the testing the first adjustable clock signal occurs when the one of the plurality of links is idle.

19. The method of claim 15, wherein the round-robin testing occurs based on a counter.

20. The method of claim 15, wherein the testing the first adjustable clock signal occurs during a CPU stall.

21. The method of claim 15, wherein the testing the first adjustable clock signal occurs periodically.

22. The method of claim 15, wherein the adjusting the first offset comprises a voltage controlled delay line.

23. The method of claim 15, wherein the adjusting the first offset comprises a digital delay line.

24. The method of claim 15, wherein the adjusting the first offset comprises an analog delay line.

25. A communication system, comprising:

means for testing an adjustable clock signal for one of a plurality of links, comprising;

means for transmitting a test pattern signal on a data line of the one of the plurality of links,

means for latching the test pattern signal based on the adjustable clock signal to generate a latched test pattern signal,

means for comparing the latched test pattern signal to the test pattern signal,

means for adjusting an offset of the adjustable clock based on the comparing; and

means for round-robin testing each of the plurality of links.