Isolation circuit

• US 20030234393A1
• Filed: 06/20/2002
• Published: 12/25/2003
• Est. Priority Date: 06/20/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cowles, Timothy B., Lunde, Aron T.
• Granted Patent: US 7,026,646 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Claims

1. An isolation circuit, comprising:

a first pad adapted to receive a control signal;

a second pad adapted to receive another signal;

a third pad coupled to a microelectronic die; and

a device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

2. The isolation circuit of claim 1, wherein the device comprises one of a metal oxide semiconductor (MOS) device, a multiplexor, a conductive jumper, ball-bond, a fuse device or an anti-fuse device.

3. The isolation circuit of claim 1, wherein at least one of the first pad, second pad and the device are formed in a scribe line of a wafer.

4. The isolation circuit of claim 1, wherein each of the first pad, the second pad, the third pad and the device are respectively formed on the microelectronic die or in a scribe area.

5. The isolation circuit of claim 1, wherein each of the first pad, the second pad and the device are respectively formed on one of a mutant die, a sacrifice die or a scribe area of a wafer.

6. An isolation circuit, comprising:

a first pad adapted to receive control signals;

a second pad adapted to receive other signals;

a third pad coupled to a microelectronic die;

a first device adapted to transfer the other signals from the second pad to the third pad in response to a predetermined control signal; and

a second device adapted to selectively prevent the second pad from being coupled to the third pad during a predetermined use of the microelectronic die.

7. The isolation circuit of claim 6, wherein the first device comprises at least one of a MOS device, a multiplexor circuit, a conductive jumper, a ball-bond, a fuse device or an anti-fuse device, and wherein the second device is adapted to inactivate the first device during the predetermined use of the microelectronic die.

8. The isolation circuit of claim 7, wherein the second device comprises one of an anti-fuse device, a ball-bond, a conductive jumper, a wireless identification circuit, and a MOS device.

9. The isolation circuit of claim 6, wherein the first device comprises an N-channel transistor and the second device inactivates the N-channel transistor by coupling a gate of the N-channel transistor to ground potential.

10. The isolation circuit of claim 6, wherein the first device comprises a P-channel transistor and the second device inactivates the P-channel transistor by coupling a gate of the P-channel transistor to a high potential.

11. The isolation circuit of claim 6, further comprising a third device to selectively disconnect the first pad from the first device.

12. The isolation circuit of claim 6, further comprising a third device to selectively connect the first pad to the first device.

13. An isolation circuit, comprising:

a wireless identification circuit;

a first pad adapted to receive a test signal;

a second pad coupled to a microelectronic die; and

a first device adapted to transfer the test signal from the first pad to the second pad in response to a signal from the wireless identification circuit.

14. The isolation circuit of claim 13, further comprising a second device to selectively inactivate the first device during a predetermined use of the microelectronic die.

15. The isolation circuit of claim 14, wherein the first device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper and a wireless identification circuit and wherein the second device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper and a wireless identification circuit.

16. An isolation circuit, comprising:

a first pad to receive a signal;

a second pad coupled to a microelectronic die;

a first device adapted to transfer the signal from the first pad to the second pad in response to a control signal; and

a second device to selectively prevent the first pad from being coupled to the second pad.

17. The isolation circuit of claim 16, further comprising a wireless identification circuit to provide the control signal.

18. The isolation circuit of claim 16, further comprising a control pad to receive the control signal.

19. An isolation circuit, comprising:

a gate control pad adapted to receive a control signal;

a plurality of test pads adapted to receive a test signal;

a plurality of part pads each coupled to a microelectronic die;

a plurality of first devices each adapted to transfer the test signal from one of the plurality of test pads to a corresponding one of the plurality of part pads in response to the control signal; and

at least one second device to selectively prevent the test pad from being coupled to the part pad.

20. The isolation circuit of claim 19, wherein each of the plurality of first devices comprises an N-channel MOS transistor and the at least one second device inactivates each of the N-channel transistors by coupling a gate of each transistor to ground potential.

21. The isolation circuit of claim 19, wherein the at least one second device comprises one of an anti-fuse, a ball-bond, a radio frequency (RF) identification circuit, and another N-channel transistor including a gate coupleable to a supply voltage during a selected use of the microelectronic die.

22. An isolation circuit, comprising:

a gate control pad adapted to receive a control signal;

a plurality of test pads adapted to receive a test signal;

a plurality of part pads each coupled to a microelectronic die;

a plurality of first devices each adapted to transfer the test signal from one of the plurality of test pads to a corresponding one of the plurality of part pads in response to the control signal;

at least one second device to selectively prevent the test pad from being coupled to the part pad; and

a plurality of third devices, each third device being adapted to selectively disconnect the gate control pad from each of the first devices.

23. The isolation circuit of claim 22, wherein each of the plurality of third devices comprises one of a fuse and a wireless identification circuit.

24. The isolation circuit of claim 22, wherein the gate control pad, the plurality of test pads and the plurality of part pads are formed in a redistribution layer.

25. An isolation circuit, comprising:

a plurality of test pads to receive test signals;

a plurality of part pads each coupled to a microelectronic die;

a plurality of first devices to couple each of the plurality of test pads to an associated one of the plurality of part pads in response to an enable signal;

an enable pad coupled to each of the first devices to receive the enable signal; and

a disable pad coupled to each of the first devices to receive a disable signal.

26. The isolation circuit of claim 25, further comprising:

a second device to connect or disconnect the enable pad from each of the first devices; and

a third device to connect or disconnect the disable pad from each of the first devices.

27. The isolation circuit of claim 26, wherein the second device and third devices each comprise one of a conductive jumper and an anti-fuse device to respectively connect the enable pad and the disable pad to each of the first devices.

28. The isolation circuit of claim 26, wherein the second and third devices each comprise a fuse to respectively disconnect the enable pad and the disable pad from each of the first devices.

29. An isolation circuit, comprising:

a first pad adapted to receive a control signal;

a second pad adapted to be coupled to a power source;

a third pad coupled to a microelectronic die; and

a device adapted to couple the second pad to the third pad in response to the control signal.

30. A microelectronic die, comprising:

a first pad adapted to receive a control signal;

a second pad adapted to receive another signal;

a third pad coupled to a component formed on the microelectronic die; and

a device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

31. The microelectronic die of claim 30, further comprising a second device adapted to selectively prevent the second pad from being coupled to the third pad during a predetermined use of the microelectronic die.

32. The microelectronic die of claim 31, wherein the second device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper, a wireless identification circuit and a fuse device.

33. The microelectronic die of claim 30, wherein the first device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper, a wireless identification circuit and a fuse device.

34. The microelectronic die of claim 30, further comprising a redistribution layer, wherein the first, second and third pads are formed in the redistribution layer.

35. A microelectronic die, comprising:

a first pad to receive a test signal during testing of at least one component formed on the microelectronic die;

a second pad coupled to the at least one component;

a first device adapted to transfer the test signal from the first pad to the second pad in response to a control signal; and

a second device to selectively prevent the first pad from being coupled to the second pad during a predetermined use of the microelectronic die.

36. The microelectronic die of claim 35, wherein the first device comprises an N-channel transistor and the second device inactivates the N-channel transistor by coupling a gate of the N-channel transistor to ground potential.

37. The microelectronic die of claim 35, wherein the first device comprises a P-channel transistor and the second device inactivates the P-channel transistor by coupling a gate of the P-channel transistor to a high potential.

38. A semiconductor wafer, comprising:

a plurality of microelectronic dies; and

at least one isolation circuit associated with each microelectronic die, the at least one isolation circuit including;

a first pad adapted to receive a control signal;

a second pad adapted to receive another signal;

a third pad coupled to the microelectronic die; and

a device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

39. The semiconductor wafer of claim 38, further comprising a second device adapted to selectively prevent the second pad from being coupled to the third pad during a predetermined use of the component.

40. The semiconductor wafer of claim 38, wherein the first device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper, a wireless identification circuit and a fuse device.

41. A semiconductor wafer, comprising:

a plurality of microelectronic dies; and

at least one isolation circuit associated with each microelectronic die, the at least one isolation circuit including;

a first pad to receive a test signal during testing of the associated microelectronic die;

a second pad coupled to the associated microelectronic die;

a first device adapted to transfer the test signal from the first pad to the second pad in response to a control signal; and

a second device to selectively prevent the first pad from being coupled to the second pad a predetermined use of the microelectronic die.

42. The semiconductor wafer of claim 41, further comprising a redistribution layer, wherein the first and second pads are formed in the redistribution layer.

43. An electronic system, comprising:

a processor; and

a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit, the isolation circuit including;

a first pad adapted to receive a control signal;

a second pad adapted to receive another signal;

a third pad coupled to one of the processor or the memory system; and

a device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

44. The electronic system of claim 43, further comprising a second device adapted to selectively prevent the second pad from being coupled to the third pad during a predetermined use of the electronic system.

45. An electronic system, comprising:

a processor; and

a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit, the isolation circuit including;

a first pad to receive a test signal during testing of the system;

a second pad coupled to the at least one of the processor and the memory system;

a first device adapted to transfer the test signal from the first pad to the second pad in response to a control signal; and

a second device to selectively prevent the first pad from being coupled to the second pad during normal operations of the electronic system.

46. The electronic system of claim 45, wherein the first device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper, a wireless identification circuit and a fuse device.

47. The electronic system of claim 45, wherein the second device comprises one of a MOS device, an anti-fuse device, a ball-bond, a conductive jumper, a wireless identification circuit and a fuse device.

48. A method of making an isolation circuit, comprising:

forming a first pad adapted to receive a control signal;

forming a second pad adapted to receive another signal;

forming a third pad coupled to a component formed in a microelectronic die; and

forming a device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

49. The method of claim 48, wherein forming the device comprises forming one of a metal oxide semiconductor (MOS) device, a multiplexor, a conductive jumper, a fuse device and an anti-fuse device.

50. The method of claim 48, wherein forming at least one of the first pad, the second pad and the device includes forming in one of a scribe line of a wafer, a mutant die of a wafer or a sacrifice die of a wafer.

51. The method of claim 48, wherein forming at least one of the first pad, the second pad and the device includes forming on the microelectronic die with the component.

52. A method of making an isolation circuit, comprising:

forming a first pad to receive a signal;

forming a second pad coupled to a component;

forming a first device adapted to transfer the signal from the first pad to the second pad in response to a control signal; and

forming a second device to selectively prevent the first pad from being coupled to the second pad.

53. The method of claim 52, further comprising providing a wireless identification circuit to provide the control signal.

54. The method of claim 52, further comprising forming a control pad coupled to the first device to receive the control signal.

55. A method of making a microelectronic die, comprising:

forming a first pad adapted to receive a control signal;

forming a second pad adapted to receive another signal;

forming a third pad coupled to a component formed on the microelectronic die; and

forming a device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

56. The method of claim 55, further comprising:

forming a second device adapted to selectively prevent the second pad from being coupled to the third pad during a predetermined use of the microelectronic die.

57. A method of making a microelectronic die, comprising:

forming a first pad to receive a signal;

forming a second pad coupled to a component;

forming a first device adapted to transfer the signal from the first pad to the second pad in response to a control signal; and

forming a second device to selectively prevent the first pad from being coupled to the second pad.

58. A method of making an electronic system, comprising:

forming a processor; and

forming a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit and wherein forming the isolation circuit includes;

forming a first pad adapted to receive a control signal;

forming a second pad adapted to receive another signal;

forming a third pad coupled to one of the processor and the memory system; and

forming a device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

59. The method of claim 58, further comprising forming a second device adapted to selectively prevent the second pad from being coupled to the third pad during a predetermined use of the electronic system.

60. A method of making an electronic system, comprising:

forming a processor; and

forming a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit and wherein forming the isolation circuit includes;

forming a first pad to receive a signal;

forming a second pad coupled to one of the processor and the memory system;

forming a first device adapted to transfer the signal from the first pad to the second pad in response to a control signal; and

forming a second device to selectively prevent the first pad from being coupled to the second pad.

61. A method, comprising:

determining if any microelectronic dies of a plurality of microelectronic dies formed on a semiconductor wafer are defective;

applying a test signal to a test pad associated with each of the microelectronic dies;

operating a device associated with each microelectronic die to couple the test pad to a part pad if the microelectronic die is good, wherein the part pad is connected to the microelectronic die; and

preventing the test signal from being applied to the microelectronic die if the die is defective.

62. The method of claim 61, wherein operating the device comprises one of:

sending a gate signal to operate a MOS transistor;

sending a signal to operate a multiplexor;

forming a conductive jumper; and

operating an anti-fuse device.

63. The method of claim 61, wherein preventing the test signal from being applied to the microelectronic die comprises one of:

sending a gate signal to prevent a MOS transistor from operating;

operating a fuse device; and

operating a multiplexor to prevent the test pad from being coupled to the part pad.

64. The method of claim 61, further comprising:

receiving a radio frequency signal to operate the device if the microelectronic die is good.

65. A method, comprising:

determining if any microelectronic dies of a plurality of microelectronic dies formed on a semiconductor wafer are defective;

applying a test signal to a test pad associated with each of the microelectronic dies;

operating a device associated with each microelectronic die to couple the test pad to a part pad associated with each microelectronic die if the microelectronic die is good, wherein the part pad is connected to the microelectronic die;

preventing the test signal from being applied to the microelectronic die if the die is defective; and

preventing each test pad from being coupled to each associated part pad during a selected use of the microelectronic die.

66. The method of claim 65, wherein the device is an N-channel transistor and wherein preventing each test pad form being coupled to each associated part pad comprises grounding a gate of the N-channel transistor.

67. The method of claim 65, wherein the device is a P-channel transistor and wherein preventing each test pad from being coupled to each associated part pad comprises applying a high signal to a gate of the P-channel transistor.