Electrical isolation between pins sharing the same tester channel

• US 20030234659A1
• Filed: 06/20/2002
• Published: 12/25/2003
• Est. Priority Date: 06/20/2002
• Status: Abandoned Application

• Current Assignee: ProMOS Technologies, Inc.
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Zieleman, Jan
• Application Number:
  US10/177,913
• Publication Number:
  US 20030234659A1
• Time in Patent Office: Days
• US Class Current: 324/762.05
• CPC Class Codes: G01R 31/319 Tester hardware, i.e. output processing circuits

Abstract

A new apparatus and method for simultaneously testing a plurality of circuit devices are achieved. The apparatus comprises, first, a tester having at least one output signal. A plurality of circuit devices is used. Each circuit device has at least one input signal. Finally, a plurality of auto-reset fuses is used. Each auto-reset fuse is coupled between the tester output signal and one of the input signals of the plurality of circuit devices. The auto-reset fuses automatically switch from low impedance during low current to high impedance during high current. The auto-reset fuses automatically switch from high impedance to low impedance after a waiting time.

Claims

1. An apparatus for simultaneously testing a plurality of circuit devices, said apparatus comprising:

a tester having at least one output signal;

a plurality of circuit devices each having at least one input signal; and

a plurality of auto-reset fuses wherein each said auto-reset fuse is coupled between said tester output signal and one of said input signals of said plurality of circuit devices, wherein said auto-reset fuses automatically switch from low impedance during low current to high impedance during high current, and wherein said auto-reset fuses automatically switch from high impedance to low impedance after a waiting time.

2. The apparatus according to claim 1 wherein said circuit devices comprise die on a semiconductor wafer.

3. The apparatus according to claim 1 wherein said circuit devices comprise packaged integrated circuit devices.

4. The apparatus according to claim 1 wherein said auto-reset fuses comprise positive temperature coefficient thermistors.

5. The apparatus according to claim 1 wherein said auto-reset fuses are placed on a probe card.

6. The apparatus according to claim 1 wherein said input signals of said circuit devices comprise bi-directional pins.

7. The apparatus according to claim 1 wherein said tester is capable of forcing a voltage on said tester output signal to test for a shorted condition.

8. An apparatus for simultaneously testing a plurality of circuit devices, said apparatus comprising:

a tester having at least one output signal;

a plurality of circuit devices each having at least one input signal; and

a plurality of auto-reset fuses wherein each said auto-reset fuse is coupled between said tester output signal and one of said input signals of said plurality of circuit devices, wherein said auto-reset fuses automatically switch from low impedance during low current to high impedance during high current, wherein said auto-reset fuses automatically switch from high impedance to low impedance after a waiting time, and wherein said auto-reset fuses comprise positive temperature coefficient thermistors.

9. The apparatus according to claim 8 wherein said circuit devices comprise die on a semiconductor wafer.

10. The apparatus according to claim 8 wherein said circuit devices comprise packaged integrated circuit devices.

11. The apparatus according to claim 8 wherein said auto-reset fuses are placed on a probe card.

12. The apparatus according to claim 8 wherein said input signals of said circuit devices comprise bi-directional pins.

13. The apparatus according to claim 8 wherein said tester is capable of forcing a voltage on said tester output signal to test for a shorted condition.

14. A method for simultaneously testing a plurality of circuit devices, said method comprising:

providing a plurality of circuit devices each having at least one input signal;

coupling a tester output signal to said input signals of said plurality of circuit devices through a plurality of auto-reset fuses wherein said auto-reset fuses automatically switch from low impedance during low current to high impedance during high current, and wherein said auto-reset fuses automatically switch from high impedance to low impedance after a waiting time; and

testing said plurality of circuit devices by forcing a voltage on said tester output wherein any shorted said input signals will be isolated by said auto-reset fuses.

15. The method according to claim 14 wherein said circuit devices comprise die on a semiconductor wafer.

16. The method according to claim 14 wherein said circuit devices comprise packaged integrated circuit devices.

17. The method according to claim 14 wherein said auto-reset fuses comprise positive temperature coefficient thermistors.

18. The method according to claim 14 wherein said auto-reset fuses are placed on a probe card.

19. The method according to claim 14 wherein said input signals of said circuit devices comprise bi-directional pins.

20. The method according to claim 14 wherein said voltage comprises one of the group consisting of:

the supply voltage for said circuit devices and the ground reference voltage of said circuit devices.