Anti-fuse sense amplifier
First Claim
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1. A sensing circuit for an anti-fuse, comprising:
- a switch operatively connected with said anti-fuse in series between a first power rail and a second power rail thereby forming a sensing node therebetween; and
an inverter having an input operatively connected to said sensing node and an output operatively connected to said switch;
wherein said switch and said inverter constitute a feedback loop so as to sense that said anti-fuse is either un-programmed or programmed.
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Abstract
An anti-fuse sensing circuit provided with no static current flowing in an anti-fuse sensing cell thereof. The sensing circuit comprises a switch and an inverter. The switch is operatively connected with an anti-fuse in series between a first power rail and a second power rail thereby forming a sensing node therebetween. The inverter is configured with an input operatively connected to the sensing node and an output operatively connected to the switch. Accordingly, the switch and the inverter constitute a feedback loop so as to sense that the anti-fuse is either un-programmed or programmed.
8 Citations
16 Claims
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1. A sensing circuit for an anti-fuse, comprising:
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a switch operatively connected with said anti-fuse in series between a first power rail and a second power rail thereby forming a sensing node therebetween; and
an inverter having an input operatively connected to said sensing node and an output operatively connected to said switch;
wherein said switch and said inverter constitute a feedback loop so as to sense that said anti-fuse is either un-programmed or programmed. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A sensing circuit for an anti-fuse, comprising:
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an NMOS switch transistor operatively connected with said anti-fuse in series between a first power rail and a second power rail thereby forming a sensing node therebetween; and
a CMOS inverter having an input operatively connected to said sensing node and an output operatively connected to a gate of said NMOS switch transistor. - View Dependent Claims (8, 9, 10, 11)
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12. A sensing circuit for an anti-fuse, comprising:
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a PMOS switch transistor operatively connected with said anti-fuse in series between a first power rail and a second power rail thereby forming a sensing node therebetween; and
a CMOS inverter having an input operatively connected to said sensing node and an output operatively connected to a gate of said PMOS switch transistor. - View Dependent Claims (13, 14, 15, 16)
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Specification