Type-II all-digital phase-locked loop (PLL)

• US 20030234693A1
• Filed: 06/19/2003
• Published: 12/25/2003
• Est. Priority Date: 06/19/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Muhammad, Khurram, Leipold, Dirk, Staszewski, Robert B.
• Granted Patent: US 7,145,399 B2
• Time in Patent Office: Days
• US Class Current: 331/16
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence

Abstract

System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL'"'"'s signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

Claims

1. A method for improving signal acquisition performance in a phase-locked loop (PLL) comprising:

acquiring a signal using a proportional loop gain circuit;

measuring an offset in the signal;

activating an integral block to accumulate an adjusted signal; and

combining outputs from the proportional loop gain circuit and the integral block to produce an oscillator tuning signal.

2. The method of claim 1, wherein the signal is a phase error.

3. The method of claim 2, wherein the adjusted signal is an adjusted phase error signal.

4. The method of claim 1, wherein the adjusted signal is the phase error combined with the offset.

5. The method of claim 4, wherein the offset is subtracted from the phase error.

6. The method of claim 1, wherein the activating further comprises adjusting a magnitude of the accumulated adjusted signal.

7. The method of claim 1, wherein the proportional loop gain circuit adjusts a magnitude of the phase error signal in multiple steps.

8. The method of claim 1, wherein the offset is known as a residue, and wherein the residue may be eliminated in the signal by setting the offset to zero.

9. The method of claim 1, wherein the oscillator tuning signal can be used to adjust the frequency of an oscillator.

10. A loop filter circuit comprising:

a proportional loop gain circuit coupled to a phase error input, the proportional loop gain circuit containing circuitry to scale a phase error signal by a first constant;

an integral loop gain block coupled to the phase error input, the integral loop gain block comprising

a residue latch coupled to the phase error input, the residue latch containing circuitry to sample an offset present in the phase error signal and to produce an adjusted phase error signal;

an integral block coupled to the residue latch, the integral block containing circuitry to accumulate the adjusted phase error signal produced by the residue latch;

a loop gain adjuster coupled to the integral block, the loop gain adjuster containing circuitry to scale the accumulated adjusted phase error signal by a second constant; and

the loop filter circuit further comprising a summing point coupled to the proportional loop gain circuit and the integral loop gain block, the summing point to combine signals from the proportional loop gain circuit and the integral loop gain block.

11. The loop filter circuit of claim 10, wherein the phase error signal is represented digitally, and wherein the proportional loop gain circuit comprises a loop gain adjuster containing circuitry to shift the phase error signal by an amount specified by the first constant.

12. The loop filter circuit of claim 11, wherein the first constant is a power of two, and wherein the shift is a whole number of bits.

13. The loop filter circuit of claim 10, wherein the residue latch comprises:

a latch coupled to the phase error input, the latch to sample the phase error input to measure the offset;

a multiplexer having a first input coupled to the phase error input and a second input coupled to the latch, the multiplexer to selectively couple its inputs to an input of the latch; and

a summing point coupled to the latch and the phase error input, the summing point to calculate the adjusted phase error signal.

14. The loop filter circuit of claim 13, wherein the adjusted phase error signal is a difference of the phase error signal and the offset.

15. The loop filter circuit of claim 10, wherein the integral block comprises:

an adder coupled to the residue latch, the adder containing circuitry to accumulate the adjusted phase error signal provided by the residue latch; and

a latch coupled to the residue latch, the latch to sample the accumulated adjusted phase error signal provided by the arithmetic unit.

16. The loop filter circuit of claim 10, wherein the integral block has a phase domain transfer function of

17. The loop filter circuit of claim 10, wherein the accumulated phase error signal is represented digitally, and wherein the loop gain contains circuitry to shift the accumulated phase error signal by an amount specified by the second constant.

18. The loop filter circuit of claim 17, wherein the second constant is a power of two, and wherein the shift is a whole number of bits.

19. The loop filter circuit of claim 10, wherein the first constant is larger than the second constant.

20. A phase-locked loop (PLL) synthesizer comprising:

a phase detector for providing a phase error signal;

an oscillator having a tuning input;

a loop filter circuit coupled to the phase detector, wherein the loop filter circuit may operate in a fast acquisition mode and subsequently switch into a type-II mode of operation, the loop filter circuit comprising

a proportional loop gain circuit coupled to the phase detector, the proportional loop gain circuit containing circuitry to scale the phase error signal by a first constant;

an integral loop gain block coupled to the phase detector, the integral loop gain block containing circuitry to scale the phase error signal by a second constant; and

a summing point coupled to the proportional loop gain circuit and the integral loop gain block, the summing point to combine signals from the proportional loop gain circuit and the integral loop gain block.

21. The PLL synthesizer of claim 20 further comprising a gain normalization circuit coupled to the loop filter circuit, the gain normalization circuit containing circuitry to normalize a tuning signal with respect to a reference frequency.

22. The PLL synthesizer of claim 20, wherein the PLL synthesizer is an all digital PLL, and wherein the first and second constants are powers of two.

23. The PLL synthesizer of claim 20, wherein the PLL synthesizer is an all digital PLL, and wherein the oscillator is a digitally controlled oscillator.

24. The PLL synthesizer of claim 20, wherein the output of the gain normalization circuit provides a tuning signal that is used to adjust an output frequency of the oscillator.

25. A wireless communications device comprising:

a radio frequency (RF) port;

an RF transceiver coupled to the RF port, the RF transceiver containing circuitry to process RF signals and a digital phase-locked loop (PLL) synthesizer coupled to the RF port, the PLL synthesizer comprising

a phase detector for providing a phase error signal;

an oscillator having an tuning input;

a loop filter circuit coupled to the phase detector, the loop filter circuit containing circuitry to provide filtering of the phase error signal, wherein the loop filter circuit may operate in a fast acquisition mode and subsequently switch into a type-II mode of operation; and

the wireless communications device further comprising a signal processing unit coupled to the RF transceiver, the signal processing unit containing circuitry to process signal streams and user usable data.

26. The wireless communications device of claim 25, wherein the wireless communications device is used in a wireless communications network.

27. The wireless communications device of claim 26, wherein the wireless communications network is a Bluetooth compliant network.

28. The wireless communications device of claim 26, wherein the wireless communications network is a cellular based communications network.