Memory storage device

• US 20030235063A1
• Filed: 06/21/2002
• Published: 12/25/2003
• Est. Priority Date: 06/21/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Van Brocklin, Andrew L., Fricke, Peter
• Granted Patent: US 6,917,532 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices

Abstract

A memory storage device includes a first and second memory cell which each have a top end and a bottom end. A first and second first dimension conductor are substantially coplanar and parallel and extend in a first dimension. The first first dimension conductor intersects the bottom end of the first memory cell and the second first dimension conductor intersects the top end of the second memory cell. A first second dimension conductor extends in a second dimension and intersects the top end of the first memory cell and a second second dimension conductor extends in the second dimension and intersects the bottom end of the second memory cell. A first third dimension conductor which extends in a third dimension is positioned between the first and second memory cell to couple the first second dimension conductor to the second second dimension conductor.

Claims

1. A memory storage device, comprising:

a first and second memory cell each having a top end and a bottom end;

a first and second first dimension conductor, wherein the first and second first dimension conductors are substantially coplanar and parallel and extend in a first dimension, wherein the first first dimension conductor intersects the bottom end of the first memory cell and the second first dimension conductor intersects the top end of the second memory cell;

a first second dimension conductor which extends in a second dimension and intersects the top end of the first memory cell;

a second second dimension conductor which extends in the second dimension and intersects the bottom end of the second memory cell; and

a first third dimension conductor which extends in a third dimension and is positioned between the first and second memory cell to couple the first second dimension conductor to the second second dimension conductor.

2. The memory storage device of claim 1, further comprising:

a first second dimension base conductor which extends in the second dimension; and

a first select switch coupled between the first third dimension conductor and the first second dimension base conductor, wherein the first select switch is configured to conduct a sense current from the first memory cell or the second memory cell to the first second dimension base conductor.

3. The memory storage device of claim 2, further comprising:

a third and fourth memory cell each having a top end and a bottom end, wherein the second first dimension conductor intersects the bottom end of the third memory cell;

a third first dimension conductor which extends in a first dimension, wherein the third first dimension conductor is positioned to be adjacent to the second first dimension conductor and not between the first first dimension conductor and the second first dimension conductor, wherein the third first dimension conductor is substantially coplanar with and parallel to the first and second first dimension conductors, wherein the third first dimension conductor intersects the top end of the fourth memory cell;

a third second dimension conductor which extends in the second dimension, wherein the third second dimension conductor is substantially coplanar with the first second dimension conductor and intersects the top end of the third memory cell;

a fourth second dimension conductor which extends in the second dimension, wherein the fourth second dimension conductor is substantially coplanar with the second second dimension conductor and intersects the bottom end of the fourth memory cell;

a second third dimension conductor extends in a third dimension and is positioned between the third and fourth memory cells to couple the third second dimension conductor to the fourth second dimension conductor; and

a second select switch coupled between the second third dimension conductor and the first second dimension base conductor, wherein the second select switch is configured to conduct a sense current from the third memory cell or the fourth memory cell to the first second dimension base conductor.

4. The memory storage device of claim 3, wherein the first and second select switches are first and second transistors.

5. The memory storage device of claim 4, wherein the first and second transistors are complementary metal-oxide semiconductor transistors.

6. The memory storage device of claim 3, wherein each memory cell includes a storage element in series with a control element.

7. The memory storage device of claim 6, wherein the storage element includes a tunnel junction device.

8. The memory storage device of claim 6, wherein the storage element includes a silicide switch.

9. The memory storage device of claim 6, wherein the storage element includes a LeCombre switch device.

10. The memory storage device of claim 6, wherein the storage element includes a rewriteable phase-change material.

11. The memory storage device of claim 6, wherein the storage element includes an anti-fuse device.

12. The memory storage device of claim 6, wherein the control element includes a tunnel junction device.

13. The memory storage device of claim 6, wherein the control element includes a diode.

14. The memory storage device of claim 6, wherein the storage element before being programmed is configured to indicate a first resistance value when a read voltage is applied across the storage element and the corresponding control element, and wherein the storage element after being programmed is configured to indicate a second resistance value when the read voltage is applied across the storage element and the corresponding control element.

15. The memory storage device of claim 6, wherein the storage element is configured to be electrically non-conductive before being programmed and is configured to be electrically conductive after being programmed.

16. The memory storage device of claim 3, wherein each memory cell includes a memory element formed with an electrically resistive material which is configured to indicate a resistance value when a read voltage is applied across the memory cell.

17. The memory storage device of claim 3, wherein each memory cell includes a resistor in series with a control element.

18. A memory array, comprising:

a first row line array extending in a first dimension;

at least two first column line segments, each disposed below the first row line array and lying along an axis which extends in a second dimension;

at least two first memory cells, wherein each first column line segment intersects at least one first memory cell and each first memory cell is intersected by a unique first row line;

at least two second column line segments, each disposed above the first row line array and aligned with corresponding first column line segments;

at least two second memory cells, wherein each second column line segment intersects at least one second memory cell and each second memory cell is intersected by the unique first row line; and

at least three conductive pillars, wherein each of the second column line segments is coupled to a pillar and the corresponding first column line segment is coupled to another pillar.

19. The memory array of claim 18, further comprising:

a second row line array extending in the first dimension, wherein the second row line array is disposed above the second column line segments and is substantially parallel to the first row line array; and

at least two third memory cells, wherein each of the second column line segments intersects at least one third memory cell and each third memory cell is intersected by a unique second row line.

20. The memory array of claim 19, further comprising:

at least two third column line segments, each disposed above the second row line array and aligned with corresponding first and second column line segments, wherein each third column line segment is coupled to a same another pillar as the corresponding first column line segment; and

at least two fourth memory cells, wherein each third column line segment intersects at least one fourth memory cell and each fourth memory cell is intersected by the unique second row line.

21. The memory array of claim 20, further comprising:

a third row line array extending in the first dimension, wherein the third row line array is disposed above the third column line segments and is substantially parallel to the first and second row line arrays; and

at least two fifth memory cells, wherein each of the third column line segments intersects at least one fifth memory cell and each fifth memory cell is intersected by a unique third row line.

22. The memory array of claim 21, further comprising:

at least two fourth column line segments, each disposed above the third row line array and aligned with corresponding first, second and third column line segments, wherein each fourth column line segment is coupled to the same pillar as the corresponding second column line segment; and

at least two sixth memory cells, wherein each fourth column line segment intersects at least one sixth memory cell and each sixth memory cell is intersected by the unique third row line.

23. The memory array of claim 22, further comprising:

a base column line extending in the second dimension; and

at least three select switches, wherein each select switch is coupled to a unique one of the at least three pillars and is configured to conduct a sense current from at least one first, second, third, fourth, fifth or sixth memory cells to the base column line.

24. The memory array of claim 23, wherein each of the select switches is a transistor coupled between the unique one of the at least three pillars and the base conductor.

25. The memory array of claim 24, wherein the transistors are complementary metal-oxide semiconductor transistors.

26. The memory array of claim 22, wherein each memory cell includes a storage element in series with a control element.

27. The memory array of claim 26, wherein the storage element includes a tunnel junction device.

28. The memory array of claim 26, wherein the storage element includes a silicide switch.

29. The memory array of claim 26, wherein the storage element includes a LeCombre switch device.

30. The memory array of claim 26, wherein the storage element includes a rewriteable phase-change material.

31. The memory array of claim 26, wherein the storage element includes an anti-fuse device.

32. The memory array of claim 26, wherein the control element includes a tunnel junction device.

33. The memory array of claim 26, wherein the control element includes a diode.

34. The memory array of claim 26, wherein the storage element before being programmed is configured to indicate a first resistance value when a read voltage is applied across the storage element and the corresponding control element, and wherein the storage element after being programmed is configured to indicate a second resistance value when the read voltage is applied across the storage element and the corresponding control element.

35. The memory array of claim 26, wherein the storage element is configured to be electrically non-conductive before being programmed and is configured to be electrically conductive after being programmed.

36. The memory array of claim 26, wherein each memory cell includes a memory element formed with an electrically resistive material which is configured to indicate a resistance value when a read voltage is applied across the memory cell.

37. The memory array of claim 22, wherein each memory cell includes a resistor in series with a control element.

38. A memory storage device, comprising:

a memory cell array;

a row line array extending in a first dimension, wherein the row line array intersects the memory cell array;

a segmented column line array extending in a second dimension, wherein each segmented column line includes at least two column lines, wherein the segmented column line array intersects the memory cell array so that each column line intersects at least one memory cell;

a conductive pillar array, wherein each conductive pillar is coupled to one column line;

a base column line array extending in the second dimension, wherein each base column line corresponds to a segmented column line; and

a select switch array, wherein each select switch is coupled between a pillar and the corresponding base column line and is configured to conduct a sense current from the at least one memory cell to the corresponding base column line.

39. The memory storage device of claim 38, wherein each of the select switches is a transistor.

40. The memory storage device of claim 39, wherein the transistors are complementary metal-oxide semiconductor transistors.

41. The memory storage device of claim 38, wherein each memory cell includes a storage element in series with a control element.

42. An integrated circuit, comprising:

a first segmented column line array extending in a second dimension, wherein each first segmented column line includes at least two first column lines;

a first memory cell array which is disposed over the first segmented column line array, wherein the first segmented column line array intersects the first memory cell array so that each first column line intersects at least one first memory cell;

a row line array extending in a first dimension, wherein the row line array is disposed over and intersects the first memory cell array;

a second memory cell array which is disposed over the first row line array, wherein the first row line array intersects the second memory cell array;

a second segmented column line array extending in a second dimension, wherein each second segmented column line includes least two second column lines, wherein the second segmented column line array is disposed over and intersects the second memory cell array so that each second column line intersects at least one second memory cell; and

a conductive pillar array, wherein each conductive pillar is coupled to one first column line and one second column line so that the one first column line and the one second column line intersect the at least one first memory cell and the at least one second memory cell which do not intersect the same row line.

43. An embedded memory for an integrated circuit, comprising:

a first segmented column line array extending in a second dimension, wherein each first segmented column line includes at least two first column lines;

a first memory cell array which is disposed over the first segmented column line array, wherein the first segmented column line array intersects the first memory cell array so that each first column line intersects at least one first memory cell;

a row line array extending in a first dimension, wherein the row line array is disposed over and intersects the first memory cell array;

a second memory cell array which is disposed over the first row line array, wherein the first row line array intersects the second memory cell array;

a second segmented column line array extending in a second dimension, wherein each second segmented column line includes least two second column lines, wherein the second segmented column line array is disposed over and intersects the second memory cell array so that each second column line intersects at least one second memory cell; and

a conductive pillar array, wherein each conductive pillar is coupled to one first column line and one second column line so that the one first column line and the one second column line intersect the at least one first memory cell and the at least one second memory cell which do not intersect the same row line.

44. A memory carrier, comprising:

at least one memory storage device, each including;

a first segmented column line array extending in a second dimension, wherein each first segmented column line includes at least two first column lines;

a first memory cell array which is disposed over the first segmented column line array, wherein the first segmented column line array intersects the first memory cell array so that each first column line intersects at least one first memory cell;

a row line array extending in a first dimension, wherein the row line array is disposed over and intersects the first memory cell array;

a second memory cell array which is disposed over the first row line array, wherein the first row line array intersects the second memory cell array;

a second segmented column line array extending in a second dimension, wherein each second segmented column line includes least two second column lines, wherein the second segmented column line array is disposed over and intersects the second memory cell array so that each second column line intersects at least one second memory cell; and

a conductive pillar array, wherein each conductive pillar is coupled to one first column line and one second column line so that the one first column line and the one second column line intersect the at least one first memory cell and the at least one second memory cell which do not intersect the same row line.

45. An electronic device, comprising:

a first segmented column line array extending in a second dimension, wherein each first segmented column line includes at least two first column lines;

a first memory cell array which is disposed over the first segmented column line array, wherein the first segmented column line array intersects the first memory cell array so that each first column line intersects at least one first memory cell;

a row line array extending in a first dimension, wherein the row line array is disposed over and intersects the first memory cell array;

a second memory cell array which is disposed over the first row line array, wherein the first row line array intersects the second memory cell array;

a second segmented column line array extending in a second dimension, wherein each second segmented column line includes least two second column lines, wherein the second segmented column line array is disposed over and intersects the second memory cell array so that each second column line intersects at least one second memory cell; and

a conductive pillar array, wherein each conductive pillar is coupled to one first column line and one second column line so that the one first column line and the one second column line intersect the at least one first memory cell and the at least one second memory cell which do not intersect the same row line.

46. The electronic device of claim 45, wherein the electronic device is a computer system.

47. A memory array, comprising:

a first row line array extending in a first dimension;

at least two first column line segments, each disposed below the first row line array and lying along an axis which extends in a second dimension;

at least two first memory cells, wherein each first column line segment intersects at least one first memory cell and each first memory cell is intersected by a unique first row line;

at least two second column line segments, each disposed above the first row line array and aligned with corresponding first column line segments;

at least two second memory cells, wherein each second column line segment intersects at least one second memory cell and each second memory cell is intersected by the unique first row line; and

means to interconnect the first and second column line segments to minimize leakage currents from the at least two first memory cells or the at least two second memory cells.

48. The memory array of claim 47, wherein the means to interconnect the first and second column line segments comprises at least three conductive pillars, wherein each of the second column line segments is coupled to a pillar and the corresponding first column line segment is coupled to another pillar.

49. The memory array of claim 48, further comprising:

a base column line extending in the second dimension; and

at least three select switches, wherein each select switch is coupled to a unique one of the at least three pillars and is configured to conduct a current from the at least two first memory cells or the at least two second memory cells intersecting the first column line segment or the second column line segment coupled to the unique one of the at least three pillars.

50. The memory array of claim 49, wherein each of the select switches is a transistor coupled between the unique one of the at least three pillars and the base column line.

51. The memory array of claim 50, wherein the transistors are complementary metal-oxide semiconductor transistors.

52. The memory array of claim 49, wherein each memory cell includes a storage element in series with a control element.

53. A memory storage device, comprising:

a first and second memory cell each having a top end and a bottom end;

a first and second conductor, wherein the first and second conductors are substantially coplanar and parallel and extend in a first dimension, wherein the first conductor intersects the bottom end of the first memory cell and the second conductor intersects the top end of the second memory cell;

a first conductor segment which extends in a second dimension and intersects the top end of the first memory cell;

a second conductor segment which extends in the second dimension and intersects the bottom end of the second memory cell;

a via positioned between the first and second memory cell to couple the first conductor segment to the second conductor segment;

a base conductor extending in the second dimension; and

means to conduct a sense current from the first memory cell or the second memory cell to the base conductor.

54. The memory storage device of claim 53, wherein the means to conduct the sense current includes a transistor coupled between the via and the base conductor.

55. The memory storage device of claim 54, wherein the transistor is a complementary metal-oxide semiconductor transistor.

56. A method of making a mass storage device, the method comprising:

forming a select switch;

forming a base conductor extending in a second dimension, wherein the select switch is coupled to the base conductor;

forming a second conductor segment which extends in the second dimension;

forming a second memory cell having a top end and a bottom end, wherein the second conductor segment intersects the bottom end of the second memory cell;

forming a first and second conductor, wherein the first and second conductors are substantially coplanar and parallel and extend in a first dimension, wherein the second conductor intersects the top end of the second memory cell;

forming a first memory cell having a top end and a bottom end, wherein the first conductor intersects the bottom end of the first memory cell;

forming a first conductor segment which extends in the second dimension and intersects the top end of the first memory cell; and

forming a via positioned between the first and second memory cell to couple the first conductor segment to the second conductor segment, wherein the select switch is coupled to the via so that the select switch can conduct a sense current from the first memory cell or the second memory cell to the base conductor.