Fine-grained gear-shifting of a digital phase-locked loop (PLL)

• US 20030235262A1
• Filed: 06/19/2003
• Published: 12/25/2003
• Est. Priority Date: 06/19/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Muhammad, Khurram, Leipold, Dirk, Staszewski, Robert B.
• Granted Patent: US 8,306,176 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence

Abstract

System and method for improving a digital PLL'"'"'s performance by making fine grained adjustments to the loop gain. A preferred embodiment comprises a plurality of loop gain adjustors (such as loop gain adjustors 605, 606, 607, and 608) that can incrementally adjust the loop gain. The incrementally adjusted loop gains are sequentially brought on-line so that the loop gain of the digital PLL is slowly decreased. By slowly decreasing the loop gain, the digital PLL is less perturbed by smaller noise transients that would take time to settle. Hence, the digital PLL can quickly acquire a signal and then decrease its loop gain and hence its bandwidth when it only needs to track a signal. The reduced bandwidth also reduces the overall noise in the digital PLL that is due to the reference noise contribution.

Claims

1. A method for adjusting a loop bandwidth for a digital phase-locked loop (PLL) comprising:

using a loop bandwidth during a signal acquisition mode of the PLL after setting it to an initial value;

reducing the loop bandwidth during a signal tracking mode of the PLL;

using the reduced loop bandwidth during a signal tracking mode of the PLL;

determining if a terminating condition has occurred; and

repeating the reducing, the second using, and the determining until the determining is true.

2. The method of claim 1, wherein the loop bandwidth can be reduced by reducing a loop gain value of a proportional gain unit of the PLL.

3. The method of claim 1, wherein the loop bandwidth can be reduced by reducing a filter bandwidth in a loop filter in the PLL.

4. The method of claim 3, wherein the reducing of the filter bandwidth in the PLL'"'"'s loop filter is performed by changing filter coefficients of an infinite impulse response (IIR) filter.

5. The method of claim 4, wherein the IIR filter is a single pole IIR filter, and wherein changing the filter coefficients comprises reducing an attenuation factor.

6. The method of claim 1, wherein the loop bandwidth can be reduced by reducing both a loop gain value of a proportional gain unit of the PLL and a filter bandwidth in a loop filter in the PLL.

7. The method of claim 1, wherein the second using is for a specified period of time, and wherein the specified period of time can vary depending on the loop bandwidth, with the smaller the loop bandwidth, the longer the specified period of time.

8. The method of claim 1, wherein the terminating condition is a number of times that the loop bandwidth has been reduced.

9. The method of claim 1, wherein the terminating condition is a value of a performance metric, and the method further comprising after the second using, calculating a performance metric.

10. The method of claim 9, wherein the determining comprises comparing the calculated performance metric against a predetermined value.

11. The method of claim 9, wherein the performance metric is a loop settling criteria.

12. The method of claim 11, wherein the loop settling criteria is a flatness of the slope of a running average of the loop'"'"'s phase error.

13. The method of claim 12, wherein the performance metric further comprises making a noise measurement of the loop'"'"'s phase error.

14. The method of claim 9, wherein the performance metric is a noise measurement of the loop'"'"'s phase error.

15. The method of claim 14, wherein the noise measurement is a mean squared value of the noise measurement.

16. The method of claim 9, wherein the performance metric is a mean of an absolute value of the loop'"'"'s phase error.

17. The method of claim 9, wherein the determining comprises comparing the calculated performance metric against a predetermined value and comparing a number of reductions performed with a maximum of reductions possible.

18. The method of claim 1, wherein the reducing is by a factor that is a power of two.

19. A loop filter circuit comprising:

a sequentially connected set of M loop gain adjustment circuits coupled to a phase error detector, wherein each loop gain adjustment circuit containing circuitry to adjust a loop gain value by a specified amount, where M is an integer;

N tuning word adjustment circuits, each tuning word adjustment circuit having a first input coupled to an input of a loop gain adjustment circuit and a second input coupled to an output of the loop gain adjustment circuit to which its first input is coupled, the tuning word adjustment circuit containing circuitry to calculate an adjusted phase error value, where N is an integer; and

a combiner having multiple inputs with one input coupled to an output from each of the tuning word adjustment circuits, the combiner containing circuitry to place a function of the inputs to an output.

20. The loop filter circuit of claim 19, wherein the adjustments made by the M loop gain adjustment circuits reduce the loop gain value.

21. The loop filter circuit of claim 19, wherein there are a greater number of loop gain adjustment circuits than a number of tuning word adjustment circuits.

22. The loop filter circuit of claim 21, wherein the number of loop gain adjustment circuits is one greater than the number of tuning word adjustment circuits.

23. The loop filter circuit of claim 19, wherein a first tuning word adjustment circuit has its first input coupled to an output of a first loop gain adjustment circuit and its second input coupled to an output of a second loop gain adjustment circuit.

24. The loop filter circuit of claim 19, wherein the loop gain adjustment circuits adjust the loop gain by a power of two value.

25. The loop filter circuit of claim 24, wherein the loop gain adjustment circuits are binary shifters.

26. The loop filter circuit of claim 25, wherein the loop gain values are represented in binary form with an order wherein a most significant bit is a leftmost bit, and wherein the binary shifters shift the loop gain value to right.

27. The loop filter circuit of claim 24, wherein the loop gain adjustment circuits perform an equal shift amount.

28. The loop filter circuit of claim 26, wherein the loop gain adjustment circuits perform a single binary bit shift.

29. The loop filter circuit of claim 19, wherein each tuning word adjustment circuit has a third input coupled to a tracking signal, and wherein when the tracking signal coupled to a tuning word adjustment circuit is active, the tuning word adjustment circuit is operating.

30. The loop filter circuit of claim 29, wherein one tracking signal is active at any given time.

31. The loop filter circuit of claim 29, wherein the tracking signals are unique.

32. The loop filter circuit of claim 29, wherein the tracking signals are also used as control signals for the combiner.

33. The loop filter circuit of claim 19, wherein at least one loop gain adjustment circuit further comprises circuitry to perform filtering upon a phase error signal provided by the phase error detector.

34. The loop filter circuit of claim 33, wherein the circuitry to perform the filtering and the circuitry to perform the loop gain value adjustment can be enabled independently of one another.

35. The loop filter circuit of claim 33, wherein the filtering is performed by an infinite impulse response (IIR) filter with an attenuation factor of λ

, wherein λ

is less than one.

36. The loop filter circuit of claim 35, wherein the IIR filter comprises:

a pair of attenuation factor adjuster circuits;

a summing point having a first input coupled to a first attenuation factor adjuster circuit and a second input coupled to a latch; and

an adder having a first input coupled to the summing point and a second input coupled to a second attenuation factor adjuster circuit and an output coupled to the latch.

37. The loop filter circuit of claim 36, wherein the IIR filter further comprises a multiplexer having a first input coupled to an input signal and a second input coupled to the output of the adder, the multiplexer to selectively couple the input signal and the output of the adder to an IIR filter output.

38. The loop filter circuit of claim 36, wherein the pair of attenuation factor adjuster circuits are set to the same attenuation.

39. The loop filter circuit of claim 19, wherein the combiner is a multiplexer.

40. The loop filter circuit of claim 19, wherein the function is selecting one input from the inputs.

41. A phase-locked loop (PLL) synthesizer comprising:

a phase detector for providing a phase error signal;

an oscillator having a tuning input; and

a loop filter circuit coupled to the phase detector, the loop filter circuit containing circuitry to adjust a loop gain value a plurality of times and calculate an adjusted phase error value each time the loop gain is adjusted.

42. The PLL synthesizer of claim 41 further comprising a gain normalization circuit coupled to the loop filter circuit, the gain normalization circuit containing circuitry to normalize a tuning signal with respect to a reference frequency.

43. The PLL synthesizer of claim 42, wherein the output of the gain normalization circuit provides the tuning signal that is used to adjust an output frequency of the oscillator.

44. The PLL synthesizer of claim 41, wherein the loop bandwidth circuit comprises:

A sequentially connected set of M loop gain adjustment circuits coupled to a phase error detector, wherein each loop gain adjustment circuit containing circuitry to adjust a loop gain value by a specified amount, where M is an integer;

N tuning word adjustment circuits, each tuning word adjustment circuit having a first input coupled to an input of a loop gain adjustment circuit and a second input coupled to an output of the loop gain adjustment circuit to which its first input is coupled, the tuning word adjustment circuit containing circuitry to calculate an adjusted phase error value, where N is an integer; and

a combiner having multiple inputs with one input coupled to an output from each of the tuning word adjustment circuits, the combiner containing circuitry to place a function of the inputs to an output.

45. The PLL synthesizer of claim 44, wherein at least one loop gain adjustment circuit further comprises circuitry to perform filtering upon a phase error signal provided by the phase error detector.

46. The PLL synthesizer of claim 45, wherein the filtering is performed by an infinite impulse response (IIR) filter with an attenuation factor of λ

, wherein λ

is less than one.

47. The PLL synthesizer of claim 41, wherein the PLL is an all-digital PLL and the oscillator is a digitally controlled oscillator.

48. The PLL synthesizer of claim 41, wherein the loop filter circuit further comprises circuitry to perform filtering upon a phase error signal provided by the phase error detector.

49. A wireless communications device comprising:

a radio frequency (RF) port;

an RF transceiver coupled to the RF port, the RF transceiver containing circuitry to process RF signals and a digital phase-locked loop (PLL) synthesizer coupled to the RF port, the PLL synthesizer comprising

a phase detector for providing a phase error signal;

an oscillator having an input;

a loop filter circuit coupled to the phase detector, the loop filter circuit containing circuitry to adjust a loop gain value a plurality of times and calculate an adjusted phase error value each time the loop gain is adjusted; and

the wireless communications device further comprising a signal processing unit coupled to the RF transceiver, the signal processing unit containing circuitry to process signal streams and user usable data.

50. The wireless communications device of claim 49, wherein the wireless communications device is used in a wireless communications network.

51. The wireless communications device of claim 50, wherein the wireless communications network is a Bluetooth compliant network.

52. The wireless communications device of claim 50, wherein the wireless communications network is a cellular based communications network.