Data transfer control device, electronic instrument, and data transfer control method

• US 20030235310A1
• Filed: 03/06/2003
• Published: 12/25/2003
• Est. Priority Date: 03/20/2002
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Saito, Nobuyuki, Oka, Yoshimi
• Granted Patent: US 7,219,238 B2
• Time in Patent Office: Days
• US Class Current: 380/281
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: H04N 21/42661 for reading from or writing on a magnetic storage medium, e.g. hard disk drive

Abstract

Data to be transferred from a BUS1 (IEEE 1394 or USB) is encrypted by a second encryption process (DES) and the encrypted data is written to an external SDRAM through an external terminal of a data transfer control device. The encrypted data that has been written to the SDRAM is read through the external terminal, and the thus-read encrypted data is transferred to a BUS2 to which an HDD is connected. Encrypted data transferred from the BUS1 is decrypted by a first decryption process (DTCP), and is written to a small-capacity SRAM within the data transfer control device. The thus-written decrypted data is read from the SRAM and encrypted by the second encryption process. Paths that bypass the second encryption (or decryption) are also provided.

Claims

1. A data transfer control device for data transfer through a bus, comprising:

a second memory access control circuit which encrypts data transferred from a first bus side in accordance with a second encryption process, and writes the thus-encrypted data to a second memory; and

a third memory access control circuit which reads the encrypted data that has been written to the second memory, and transfers the thus-read encrypted data to a second bus side where a storage medium is connected.

2. The data transfer control device as defined in claim 1, wherein:

the second memory is provided outside the data transfer control device;

the data transfer control device further includes an external terminal for connection with the external second memory;

the second memory access control circuit writes the encrypted data to the second memory through the external terminal; and

the third memory access control circuit reads the encrypted data which has been written to the second memory, through the external terminal.

3. The data transfer control device as defined by claim 1, wherein:

the second memory access control circuit encrypts isochronous data among data transferred from the first bus side, in accordance with the second encryption process, and writes the thus-encrypted isochronous data to the second memory.

4. The data transfer control device as defined in claim 1, further comprising:

a first memory access control circuit which decrypts data by a first decryption process, and writes the decrypted data to a first memory provided within the data transfer control device, the data having been encrypted by a first encryption process and then transferred from the first bus side,

wherein the second memory access control circuit reads the data that has been written to the first memory, encrypts the thus-read data by the second encryption process, and writes the encrypted data to the second memory.

5. The data transfer control device as defined in claim 4, wherein:

a storage area of the first memory includes an isochronous data area in which isochronous data is stored and another area;

the first memory access control circuit decrypts isochronous data which has been encrypted by a first encryption process and then transferred from the first bus side, by the first decryption process, and writes the decrypted isochronous data to the isochronous data area in the first memory; and

the second memory access control circuit reads the thus-written isochronous data in the isochronous data area of the first memory, encrypts the thus-read isochronous data by the second encryption process, and writes the encrypted isochronous data to the second memory.

6. The data transfer control device as defined in claim 1, wherein:

the second memory access control circuit bypasses the second encryption process for data that does not require encryption, and writes the data into the second memory.

13. The data transfer control device as defined in claim 1,

wherein the second memory is a synchronized type of memory that is capable of inputting and outputting data having sequential addresses in synchronization with a clock.

14. The data transfer control device as defined in claim 4,

wherein the second memory is a synchronized type of memory that is capable of inputting and outputting data having sequential addresses in synchronization with a clock.

17. An electronic instrument comprising:

the data transfer control device as defined in claim 1;

and

a storage medium connected to the second bus, for storing data transferred through the second bus.

18. An electronic instrument comprising:

the data transfer control device as defined in claim 4;

and

a storage medium connected to the second bus, for storing data transferred through the second bus.

7. A data transfer control device for data transfer through a bus, comprising:

a third memory access control circuit which writes data to a second memory, the data having been encrypted by a second encryption process and transferred from a second bus side to which is connected a storage medium; and

a second memory access control circuit which reads the encrypted data that has been written to the second memory, decrypts the thus-read data by a second decryption process, and transfers the decrypted data to a first bus side.

8. The data transfer control device as defined in claim 7, wherein:

the second memory is provided outside the data transfer control device;

the data transfer control device further includes an external terminal for connection with the second memory;

the third memory access control circuit writes data which has been transferred from the second bus side, to the external second memory through the external terminal; and

the second memory access control circuit reads the encrypted data which has been written to the second memory, through the external terminal.

9. The data transfer control device as defined by claim 7,

wherein the third memory access control circuit writes isochronous data from among data which has been transferred from the second bus side to which is connected a storage medium, to the second memory.

10. The data transfer control device as defined in claim 7, further comprising:

a first memory access control circuit, wherein;

the second memory access control circuit reads encrypted data that has been written to the second memory, decrypts the thus-read data by the second decryption process, and writes the decrypted data to a first memory; and

the first memory access control circuit reads data that has been written to the first memory, -encrypts the thus-read data by a first encryption process, and transfers the encrypted data to the first bus side.

11. The data transfer control device as defined in claim 10, wherein:

a storage area of the first memory includes an isochronous data area in which isochronous data is stored and another area;

the second memory access control circuit reads encrypted isochronous data that has been written to the second memory, decrypts the thus-read isochronous data by the second decryption process, and writes the decrypted isochronous data to the isochronous data area in the first memory; and

the first memory access control circuit reads the isochronous data that has been written to the isochronous data area of the first memory, encrypts the thus-read isochronous data by the first encryption process, and transfers the encrypted isochronous data to the first bus side.

12. The data transfer control device as defined in claim 7,

wherein the second memory access control circuit bypasses the second decryption process for data that does not require decryption, and transfers the data to the first bus side.

15. The data transfer control device as defined in claim 7,

wherein the second memory is a synchronized type of memory that is capable of inputting and outputting data having sequential addresses in synchronization with a clock.

16. The data transfer control device as defined in claim 11,

wherein the second memory is a synchronized type of memory that is capable of inputting and outputting data having sequential addresses in synchronization with a clock.

19. An electronic instrument comprising:

the data transfer control device as defined in claim 7;

and

a storage medium connected to the second bus, for storing data transferred through the second bus.

20. An electronic instrument comprising:

the data transfer control device as defined in claim 11;

and

a storage medium connected to the second bus, for storing data transferred through the second bus.

21. A data transfer control method for data transfer through a bus, comprising:

encrypting data transferred from a first bus side, by a second encryption process, and writing the encrypted data to a second memory provided outside a data transfer control device, through an external terminal of the data transfer control device; and

reading the encrypted data that has been written to the second memory, through the external terminal of the data transfer control device, and transferring the thus-read data to a second bus side to which is connected a storage medium.

22. A data transfer control method for data transfer through a bus, comprising:

writing data to a second memory provided outside a data transfer control device, through an external terminal of the data transfer control device, the data having been encrypted by a second encryption process and transferred from a second bus side to which is connected a storage medium; and

reading the encrypted data that has been written to the second memory, through the external terminal of the data transfer control device, decrypting the thus-read data by a second decryption process, and transferring the decrypted data to a first bus side.