Notched damascene planar poly/metal gate and methods thereof

• US 20030235943A1
• Filed: 01/02/2003
• Published: 12/25/2003
• Est. Priority Date: 06/20/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Trivedi, Jigish D.
• Granted Patent: US 7,078,284 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Methods for forming notched gates and semiconductor devices utilizing the notched gates are provided. The methods utilize the formation of a dummy gate on a substrate. The dummy gate is etched to form notches in the dummy gate, and sidewall spacers are formed on the sidewalls of the notched dummy gate. The dummy gate is removed, and a notched gate is formed. The methods allow the height and depth of the notches to be independently controlled, and transistors having shorter channel lengths are formed.

Claims

1. A method of forming a notched gate comprising:

supplying a substrate;

forming a dummy gate on said substrate, said dummy gate having sidewalls;

etching said dummy gate to form laterally recessed notches in said dummy gate;

forming sidewall spacers on said sidewalls of said dummy gate;

removing said dummy gate to form a recess between said sidewall spacers;

forming a gate oxide in said recess; and

depositing a permanent gate material in said recess to form a notched gate.

2. A method of forming a notched gate comprising:

supplying a substrate;

forming a dummy gate on said substrate, said dummy gate having sidewalls;

etching said dummy gate to form laterally recessed notches in said dummy gate;

forming sidewall spacers on said sidewalls of said dummy gate;

depositing a layer of dielectric material over said dummy gate;

removing the dielectric material overlying said dummy gate;

removing said dummy gate to form a recess between said sidewall spacers;

forming a gate oxide in said recess; and

depositing a permanent gate material in said recess to form a notched gate.

3. A method of forming a notched gate comprising:

supplying a substrate;

forming a well region in said substrate;

forming at least one isolation region in said substrate;

forming a dummy gate on said substrate over said well region, said dummy gate having sidewalls;

etching said dummy gate to form laterally recessed notches in said dummy gate;

forming extension regions in said well region after etching said dummy gate, said extension regions formed within said well region adjacent to said dummy gate;

forming sidewall spacers on said sidewalls of said dummy gate;

forming doped regions in said well region adjacent to said sidewall spacers;

depositing a layer of dielectric material over said dummy gate;

removing the dielectric material overlying said dummy gate;

removing said dummy gate to form a recess between said sidewall spacers;

forming a gate oxide in said recess; and

depositing a permanent gate material in said recess to form a notched gate.

4. The method as claimed in claim 3 further comprising providing at least one pocket implant within said well region under said extension regions.

5. The method as claimed in claim 3 wherein said at least one isolation region comprises an isolation trench.

6. The method as claimed in claim 3 wherein said layer of dielectric material is formed by depositing an inter-layer dielectric material over said substrate and said dummy gate.

7. The method as claimed in claim 3 wherein said doped regions and said extension regions comprise source/drain regions.

8. A method of forming a notched gate comprising:

supplying a substrate;

forming a dummy gate on said substrate, said dummy gate having sidewalls, wherein said dummy gate comprises at least one layer;

etching one of said at least one layers to form laterally recessed notches in said dummy gate;

forming sidewall spacers on said sidewalls of said dummy gate;

removing said dummy gate to form a recess between said sidewall spacers;

forming a gate oxide in said recess; and

depositing a permanent gate material in said recess to form a notched gate.

9. A method of forming a notched gate comprising:

supplying a substrate;

forming a dummy gate on said substrate, said dummy gate having sidewalls, wherein said dummy gate comprises at least one layer;

etching one of said at least one layers to form laterally recessed notches in said dummy gate;

forming sidewall spacers on said sidewalls of said dummy gate;

depositing a layer of dielectric material over said dummy gate;

removing the dielectric material overlying said dummy gate;

removing said dummy gate to form a recess between said sidewall spacers;

forming a gate oxide in said recess; and

depositing a permanent gate material in said recess to form a notched gate.

10. A method of forming a notched gate comprising:

supplying a substrate;

forming a well region in said substrate;

forming at least one isolation region in said substrate;

forming a dummy gate on said substrate over said well region, said dummy gate having sidewalls, wherein said dummy gate comprises at least one layer;

etching one of said at least one layers to form laterally recessed notches in said dummy gate;

forming extension regions in said well region after etching said dummy gate, said extension regions formed within said well region adjacent to said dummy gate;

forming sidewall spacers on said sidewalls of said dummy gate;

forming doped regions in said well region adjacent to said sidewall spacers;

depositing a layer of dielectric material over said dummy gate;

removing the dielectric material overlying said dummy gate;

removing said dummy gate to form a recess between said sidewall spacers;

forming a gate oxide in said recess; and

depositing a permanent gate material in said recess to form a notched gate.

11. A method of controlling the notch dimensions of a damascene notched gate comprising:

forming a dummy gate over a substrate, said dummy gate having sidewalls;

etching said dummy gate to form laterally recessed notches in said dummy gate, wherein said etch is controlled to select the depth of said laterally recessed notches;

forming sidewall spacers on said sidewalls of said dummy gate;

removing said dummy gate to form a recess between said sidewall spacers; and

depositing a permanent gate material in said recess to form a notched gate.

12. The method as claimed in claim 11 wherein said depth is in the range of about 50 to about 200 Å

.

13. A method of controlling the notch dimensions of a damascene notched gate comprising:

forming a dummy gate over a substrate, said dummy gate having sidewalls, wherein said dummy gate comprises at least one layer having a selected thickness;

etching said dummy gate to form laterally recessed notches in said dummy gate, wherein said etch is controlled to select the depth of said laterally recessed notches, and wherein the height of said laterally recessed notches is determined by said selected thickness of one of said at least one layers;

forming sidewall spacers on said sidewalls of said dummy gate;

removing said dummy gate to form a recess between said sidewall spacers; and

depositing a permanent gate material in said recess to form a notched gate.

14. The method as claimed in claim 13 wherein said height is in the range of about 100 to about 500 Å

.

15. The method as claimed in claim 13 wherein said height is in the range of about 100 to about 500 Å

and said depth is in the range of about 50 to about 200 Å

.

16. A method of forming a notched gate comprising:

supplying a substrate;

forming a dummy gate on said substrate, said dummy gate having sidewalls, wherein said dummy gate comprises;

a first layer proximate to said substrate, wherein said first layer comprises a first dielectric layer;

a second layer proximate to said first layer; and

a third layer proximate to said second layer;

etching said second layer to form laterally recessed notches in said dummy gate;

forming sidewall spacers on said sidewalls of said dummy gate;

depositing a layer of dielectric material over said dummy gate;

removing the dielectric material overlying said dummy gate;

removing said dummy gate to form a recess between said sidewall spacers;

forming a gate oxide in said recess; and

depositing a permanent gate material in said recess to form a notched gate.

17. The method as claimed in claim 16 wherein said step of etching said second layer comprises a wet etch, and wherein said first dielectric layer is selected to be resistant to said wet etch.

18. The method as claimed in claim 16 wherein said first dielectric layer is selected from gate oxide, silicon nitride, aluminum oxide, silicon carbide, hafnium oxide, and combinations thereof.