Memory defect redress analysis treating method, and memory testing apparatus performing the method

• US 20030236648A1
• Filed: 04/11/2003
• Published: 12/25/2003
• Est. Priority Date: 10/19/2000
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Yasui, Takahiro
• Granted Patent: US 6,907,385 B2
• Time in Patent Office: Days
• US Class Current: 702/185
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

There are provided a failure repair analyzing and processing method and a memory testing apparatus provided with a failure repair analyzing and processing apparatus using this method, that are capable of reducing a time duration required to perform the failure repair analysis and processing for a multi-bit memory having redundancy structure. A plurality of repair analysis units as well as a common failure analysis memory are provided, and these repair analysis units are concurrently operated in parallel with each other, thereby to carry out respective repair analyses and processings for failure memory cells of plural data bits read out from the failure analysis memory in the plural repair analysis units concurrently and in parallel with each other. As a result, a time duration required to execute the failure repair analysis and processing is shortened.

Claims

1. A method of analyzing and processing a repair of failure that is carried out in a memory testing apparatus which comprises:

a failure analysis memory for storing therein failure data representing a failure memory cell or cells of a memory under test having redundancy structure; and

a failure repair analyzing and processing apparatus for analyzing as to whether the failure memory cell or cells of the memory under test can be repaired on the basis of the failure data read out from the failure analysis memory after the testing has been completed, said method comprising the steps of;

reading out failure data respectively from plural specified data bit memory areas of the failure analysis memory in sequence and distributing them to corresponding plural repair analysis units respectively; and

operating concurrently the plural repair analysis units in parallel with each other and causing the units to carry out concurrently their repair analyses and processings for the failure memory cell or cells corresponding to the failure data read out from the failure analysis memory in parallel with each other.

2. The method of analyzing and processing a repair of failure as set forth in claim 1, further including:

the step of checking whether there exists an unprocessed data bit memory area for which the repair analysis and processing is not executed or not, and wherein

in case an unprocessed data bit memory area has been detected, each of the repair analysis units performs, when it has completed the repair analysis and processing for failure data of a data bit memory area assigned to that unit, the repair analysis and processing for failure data of the detected unprocessed data bit memory area at once.

3. The method of analyzing and processing a repair of failure as set forth in claim 1 or 2, wherein said step of reading out failure data respectively from plural specified data bit memory areas of the failure analysis memory in sequence includes the step of:

switching in sequence respective address signals accessing to plural specified data bit memory areas, that are outputted respectively from the plural repair analysis units to apply them to the failure analysis memory; and

wherein the period that the plural address signals are switched in sequence is a period that the period of each address signal accessing to corresponding one specified data bit memory area is divided by the number of specified data bit memory areas; and

wherein the failure data read out from the failure analysis memory are failure data that are switched in sequence at intervals of the same period as the switching period of the address signals applied to the failure analysis memory.

4. A memory testing apparatus comprising:

a failure analysis memory for storing therein failure data representing a failure memory cell or cells of a memory under test having redundancy structure;

a plurality of repair analysis units, each being constructed such that it specifies any data bit memory area in plural data bit memory areas of the failure analysis memory, reads out failure data stored in the specified data bit memory area in respective failure data stored in the plural data bit memory areas of the failure analysis memory, and analyzes as to whether a memory cell array or arrays associated with the read-out failure data can be repaired or not;

access control means for switching in sequence respective address signals outputted from the plural repair analysis units to apply them to the failure analysis memory in sequence;

data distributing means for distributing respective failure data read out from the plural specified data bit memory areas of the failure analysis memory to the corresponding plural repair analysis units, respectively; and

a control part that controls respective repair analysis and processing operations of the plural repair analysis units.

5. The memory testing apparatus as set forth in claim 4, wherein each of the plural repair analysis units is provided with its own address generator, and each repair analysis unit can access the failure analysis memory separately and independently of the operation of other repair analysis unit or units by generating an address signal accessing to a specified data bit memory area from its own address generator.

6. The memory testing apparatus as set forth in claim 4, wherein the access control means is arranged such that it switches in sequence respective address signals accessing to plural specified data bit memory areas, that are outputted respectively from the plural repair analysis units to apply them to the failure analysis memory;

and

wherein the period that the plural address signals are switched in sequence is a period that the period of each address signal accessing to corresponding one specified data bit memory area is divided by the number of specified data bit memory areas; and

wherein the failure data read out from the failure analysis memory are failure data that are switched in sequence at intervals of the same period as the switching period of the address signals applied to the failure analysis memory.

7. The memory testing apparatus as set forth in any one of claim 4, 5 or 6, wherein the control part applies respective analysis start signals, respective bit specified signals, and respective load signals to the plural repair analysis units, respectively, and receives a analysis end signal from each of the plural repair analysis units, thereby to control respective repair analysis and processing operations of the plural repair analysis units;

and

the control part further comprises;

unprocessed data bit detecting means for detecting, each time a repair analysis unit that has completed the repair analysis and processing operation for a memory cell array or arrays associated with failure data of a specified data bit memory area transmits an analysis end signal, whether there exists an unprocessed data bit memory area for which the repair analysis and processing is not executed or not; and

data bit update means for updating, in case an unprocessed data bit memory area has been detected, a bit specifying signal being applied to a repair analysis unit that has completed the repair analysis and processing operation to a bit specifying signal to be applied to the unprocessed data bit memory area.

8. The memory testing apparatus as set forth in any one of claim 4, 5 or 6, wherein the memory under test is a multi-bit memory;

and

wherein the failure analysis memory includes at least the same number of data bit memory areas as the number of bits of the memory under test, and failure data of each of the data bits of the multi-bit memory under test are stored in corresponding one data bit memory area of the failure analysis memory.

9. The memory testing apparatus as set forth in any one of claim 4, 5 or 6, wherein the memory under test is a one-bit memory;

and

wherein the failure analysis memory includes at least the same number of data bit memory areas as the number of memory cell arrays of the memory under test, and failure data of each of the memory cell arrays of the memory under test are stored in corresponding one data bit memory area of the failure analysis memory.