Characterization and verification for integrated circuit designs
First Claim
1. A method comprising characterizing variations in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations.
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Accused Products
Abstract
Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.
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Citations
71 Claims
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1. A method comprising
characterizing variations in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations.
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5. A method comprising
using a pattern-dependent model of topographical variation to predict feature dimension variations or electrical characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topological variation, and verifying that the predicted feature dimensions or electrical characteristics conform to the design.
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6. A method comprising
using a pattern-dependent model of topographical variation to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes lithography or etch, and verifying that the predicted characteristics conform to the design, the characteristics including feature dimensions or electrical characteristics.
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36. A method comprising
using a pattern-dependent model to predict variations in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes a fabrication process that will impart topographical variation to the integrated circuit.
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43. A method comprising
using a pattern-dependent model to predict feature dimension characteristics of a level of an integrated circuit that is to be fabricated in accordance with a design, and certifying that the predicted feature dimension characteristics meet specifications of the design.
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49. A method comprising
using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, and certifying that the predicted characteristics meet specifications of the design.
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50. A method comprising
using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a subsequent lithography or etch process, and certifying that the predicted characteristics resulting from the process up to the lithography or etch process will meet specifications of the design.
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51. A method comprising
applying a lithographic or etching process to a test wafer, deriving, from the processed test wafer, characterization information about variations of feature dimensions resulting from the lithographic or etching process, and using the characterization information in a pattern-dependent model of the lithographic or etching process.
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52. A method comprising
using a pattern-dependent model to predict relative variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by processes that respectively include different lithographic or etching tools or consumables, and selecting one of the processes for use in fabricating the integrated circuit based on the relative predicted variations.
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58. A method comprising
using a pattern-dependent model to verify that chip-level features of a design of an integrated circuit can be manufactured within focus limitations of a lithographic tool.
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62. A method comprising
using a pattern-dependent model to predict whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design, and if not, adjusting the design or processing parameters so that it can be.
Specification