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Characterization and verification for integrated circuit designs

  • US 20030237064A1
  • Filed: 12/17/2002
  • Published: 12/25/2003
  • Est. Priority Date: 06/07/2002
  • Status: Active Grant
First Claim
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1. A method comprising characterizing variations in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations.

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