Characterization and verification for integrated circuit designs

• US 20030237064A1
• Filed: 12/17/2002
• Published: 12/25/2003
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Praesagus Inc. (Cadence Group)
• Inventors: White, David, Smith, Taber H.
• Granted Patent: US 7,174,520 B2
• Time in Patent Office: Days
• US Class Current: 716/136
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]

Abstract

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Claims

1. A method comprising

characterizing variations in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations.

2. The method of claim 1 in which the process that produces topographical variation comprises electroplated copper deposition or chemical mechanical polishing.

3. The method of claim 1 in which the process includes a lithographic or etching process that interacts with the topographical variation to produce the variations in feature dimensions.

4. The method of claim 3 in which the etching process comprises a plasma etching process.

33. The method of claim 1 in which the characterizing is provided as a service in a network.

34. The method of claim 33 in which the network comprises an intranet, an extranet, or an internet, and the characterizing is provided in response to user requests.

35. The method of claim 1 also including using an electronics design automation (EDA) tool in conjunction with the characterizing.

57. The method of claim 1, 5, 6, 36, 51, or 52 in which the feature dimensions are measured by scanning electron microscopy (SEM), scatterometry and scanning probe microscopy, line edge roughness (LER) tools, or three-dimensional measurement techniques.

5. A method comprising

using a pattern-dependent model of topographical variation to predict feature dimension variations or electrical characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topological variation, and

verifying that the predicted feature dimensions or electrical characteristics conform to the design.

6. A method comprising

using a pattern-dependent model of topographical variation to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes lithography or etch, and

verifying that the predicted characteristics conform to the design,

the characteristics including feature dimensions or electrical characteristics.

7. The method of claim 6 in which the process includes plasma etch and the characteristics include sidewall angle, trench width, or trench depth.

8. The method of claim 6 in which the characteristics include feature dimensions.

9. The method of claim 6 in which the characteristics include electrical characteristics.

10. The method of claim 6 in which the process includes electroplated copper deposition.

11. The method of claim 6 in which the process includes chemical mechanical polishing.

12. The method of claim 6 in which the characteristics comprise feature width.

13. The method of claim 6 in which the characteristics are associated with all of the integrated circuit.

14. The method of claim 6 in which the characteristics are associated with less than all of the integrated circuit.

15. The method of claim 6 in which the verifying of the predicted characteristics includes verifying feature widths.

16. The method of claim 6 in which the verifying of the predicted characteristics also includes verifying the topographical variation.

17. The method of claim 6 in which the verifying of the predicted characteristics includes verifying physical and electrical parameters that result from feature width variation.

18. The method of claim 6 in which the prediction or verification is done in response to a request received electronically from a network.

19. The method of claim 6 in which the prediction or verification is provided as a web service.

20. The method of claim 6 in which using a pattern-dependent model of topographical variation to predict characteristics of the integrated circuit includes using the model with respect to at least two different process features.

21. The method of claim 20 in which the process features comprise process recipes.

22. The method of claim 21 in which the process recipes include different tool settings for a tool.

23. The method of claim 21 in which the process recipes include power settings.

24. The method of claim 21 in which the process recipes include etch times.

25. The method of claim 21 in which the process recipes include polish times.

26. The method of claim 21 in which the process recipes include deposition times.

27. The method of claim 21 in which the process recipes include pressures.

28. The method of claim 20 in which the process features comprise tools.

29. The method of claim 28 in which the tools comprise tools made by two different vendors.

30. The method of claim 20 in which the process features comprise consumables.

31. The method of claim 30 in which the consumables comprise photoresists or mask types.

32. The method of claim 20 in also including choosing among the process features based on the predictions.

36. A method comprising

using a pattern-dependent model to predict variations in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that includes a fabrication process that will impart topographical variation to the integrated circuit.

37. The method of claim 36 in which the fabrication process comprises electroplated copper deposition (ECD).

38. The method of claim 36 in which the fabrication process comprises chemical mechanical polishing (CMP).

39. The method of claim 36 in which the model predicts variations in feature dimension resulting from interaction between the fabrication process and a lithography or etch process.

40. The method of claim 36 in which the predicting is provided as a service in a network.

41. The method of claim 40 in which the network comprises an intranet, an extranet, or an internet, and the predicting is provided in response to user requests.

42. The method of claim 36 also including using an electronics design automation (EDA) tool in conjunction with the predicting.

43. A method comprising

using a pattern-dependent model to predict feature dimension characteristics of a level of an integrated circuit that is to be fabricated in accordance with a design, and

certifying that the predicted feature dimension characteristics meet specifications of the design.

44. The method of claim 43 also including adding a circuit component to the design after the feature dimension characteristics are predicted, and, after the component is added to the design, certifying that the predicted feature dimension characteristics meet the design specifications.

45. The method of claim 43 in which the dimension comprises feature width.

46. The method of claim 43 in which the predicting and certifying are provided as a service in a network.

47. The method of claim 46 in which the network comprises an intranet, an extranet, or an internet, and the predicting and certifying are provided in response to user requests.

48. The method of claim 43 also including using an electronics design automation (EDA) tool in conjunction with the predicting and the certifying.

49. A method comprising

using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch process, and

certifying that the predicted characteristics meet specifications of the design.

56. The method of claim 6, 49, 50, 51, or 52 in which the lithography comprises deep ultra-violet (DUV), extremely short UV (EUV), or ion projection lithography (IPL).

50. A method comprising

using a pattern-dependent model to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process that includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a subsequent lithography or etch process, and

certifying that the predicted characteristics resulting from the process up to the lithography or etch process will meet specifications of the design.

51. A method comprising

applying a lithographic or etching process to a test wafer,

deriving, from the processed test wafer, characterization information about variations of feature dimensions resulting from the lithographic or etching process, and

using the characterization information in a pattern-dependent model of the lithographic or etching process.

52. A method comprising

using a pattern-dependent model to predict relative variations of feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by processes that respectively include different lithographic or etching tools or consumables, and

selecting one of the processes for use in fabricating the integrated circuit based on the relative predicted variations.

53. The method of claim 52 in which the predicting is provided as a service in a network.

54. The method of claim 53 in which the network comprises an intranet, an extranet, or an internet, and the predicting is provided in response to user requests.

55. The method of claim 52 also including using an electronics design automation (EDA) tool in conjunction with the predicting.

58. A method comprising

using a pattern-dependent model to verify that chip-level features of a design of an integrated circuit can be manufactured within focus limitations of a lithographic tool.

59. The method of claim 58 in which the verifying is provided as a service in a network.

60. The method of claim 59 in which the network comprises an intranet, an extranet, or an internet, and the verifying is provided in response to user requests.

61. The method of claim 58 also including using an electronics design automation (EDA) tool in conjunction with the verifying.

62. A method comprising

using a pattern-dependent model to predict whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design, and

if not, adjusting the design or processing parameters so that it can be.

63. The method of claim 62 in which the adjusting includes selecting optimal tool settings of a lithography tool.

64. The method of claim 62 in which the adjusting includes selecting optimal photoresist materials.

65. The method of claim 62 in which the adjusting includes selecting optimal photoresist deposition recipes.

66. The method of claim 62 in which the adjusting includes adjusting tool settings for a tool.

67. The method of claim 62 in which the adjusting includes adjusting power settings.

68. The method of claim 62 in which the adjusting includes adjusting etch times.

69. The method of claim 62 in which the adjusting includes adjusting polish times.

70. The method of claim 62 in which the adjusting includes adjusting deposition times.

71. The method of claim 62 in which the adjusting includes adjusting include pressures.