Systems and methods for generating an artwork representation according to a circuit fabrication process
First Claim
1. A system for generating an artwork representation according to a circuit fabrication process, comprising:
- a cell library that stores at least dimensional information associated with a plurality of circuit cells, wherein each of said plurality of circuit cells is defined by a sub-mask for a respective logical device according to said circuit fabrication process;
an instance placement engine that generates a circuit layout that is defined by at least a specification file specifying an arrangement of logical devices and said cell library; and
an artwork generator that generates an artwork representation that defines a mask for etching of said generated circuit layout according to said circuit fabrication process.
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Accused Products
Abstract
In one embodiment, the present invention relates to a system for generating an artwork representation according to a circuit fabrication process. The system comprises a cell library that stores at least dimensional information associated with a plurality of circuit cells, wherein each of the plurality of circuit cells is defined by a sub-mask for a respective logical device according to the circuit fabrication process; an instance placement engine that generates a circuit layout that is defined by at least a specification file specifying an arrangement of logical devices and the cell library; and an artwork generator that generates an artwork representation that defines a mask for etching of the generated circuit layout according to the circuit fabrication process.
15 Citations
29 Claims
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1. A system for generating an artwork representation according to a circuit fabrication process, comprising:
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a cell library that stores at least dimensional information associated with a plurality of circuit cells, wherein each of said plurality of circuit cells is defined by a sub-mask for a respective logical device according to said circuit fabrication process;
an instance placement engine that generates a circuit layout that is defined by at least a specification file specifying an arrangement of logical devices and said cell library; and
an artwork generator that generates an artwork representation that defines a mask for etching of said generated circuit layout according to said circuit fabrication process. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for generating an artwork representation according to a circuit fabrication process, comprising:
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receiving a specification file defining an arrangement of logical devices;
accessing a cell library to retrieve circuit cell dimensional information defined by sub-masks of said logical devices according to said circuit fabrication process; and
generating an artwork representation of a circuit according to said circuit fabrication process utilizing at least said specification file and said circuit cell dimensional information. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A system for generating an artwork representation according to a circuit fabrication process, comprising:
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means for storing at least dimensional information associated with a plurality of circuit cells, wherein each of said plurality of circuit cells is defined by a sub-mask for a respective logical device according to said circuit fabrication process;
means for generating a circuit layout that is defined by at least a specification file specifying an arrangement of logical devices and said cell library; and
means for generating an artwork representation that defines a mask for etching of said generated circuit layout according to said circuit fabrication process. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29)
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Specification