System and method for improved register allocation in an optimizing compiler

• US 20030237080A1
• Filed: 06/19/2002
• Published: 12/25/2003
• Est. Priority Date: 06/19/2002
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Thompson, Carol, Srinivasan, Uma
• Application Number:
  US10/177,343
• Publication Number:
  US 20030237080A1
• Time in Patent Office: Days
• US Class Current: 717/161
• CPC Class Codes: G06F 8/441 Register allocation; Assignment of physical memory space to logical memory space
• CPC Class Codes: G06F 8/4441 Reducing the execution time required by the program code
• CPC Class Codes: G06F 8/4452 Software pipelining

Abstract

Systems and methods for improving an optimizing compiler are disclosed. A representative compiler, includes: a translation engine and a low-level instruction optimizer, the low-level instruction optimizer further includes a scheduler and register allocator, the scheduler and register allocator comprising: a minimum initiation interval determiner; a modulo scheduler; a rotating register allocator configured to receive a schedule, allocate and assign rotating registers responsive to modulo schedule, and communicate a status of a set of rotating registers; a static register allocator configured to receive the schedule, allocate and assign scalar variables to a set of scalar registers responsive to the modulo schedule and the status; and a rotating register spiller configured to receive and store interfering variables in a memory. A representative method includes the following steps: identifying a plurality of variables having a lifetime that exceeds an initiation interval; allocating a rotating register for each of the identified plurality of variables; assigning one of the plurality of variables to a respective rotating register when the variable was initiated within the source code programming loop; and communicating rotating register usage to a scalar register allocator, wherein the scalar register allocator assigns variables outside of the source code programming loop to an allocated but unassigned rotating register.

Claims

1. A method for improving register allocation in an optimizing compiler, comprising:

identifying a plurality of variables having a lifetime that exceeds an initiation interval of a present source code programming loop of interest;

allocating a rotating register for each of the identified plurality of variables;

assigning one of the plurality of variables to a respective rotating register when the variable was initiated within the source code programming loop; and

communicating rotating register usage to a scalar register allocator, wherein the scalar register allocator assigns variables outside of the source code programming loop to an allocated but unassigned rotating register.

2. The method of claim 1, further comprising:

inserting placeholders in the schedule, the placeholders identifying a location for spill code.

3. The method of claim 2, wherein the placeholder comprises a no-operation (NOP).

4. The method of claim 1, further comprising:

recognizing a pipeline processed intermediate representation of the source code; and

managing a scalar register allocator to minimize an amount of spill code generated within the loop of interest.

5. The method of claim 1, further comprising:

recognizing scalar lifetime values overwritten within the loop to generate a set of scalar lifetime values; and

reassigning the set of scalar lifetime values to static registers for the duration of the source code programming loop.

6. The method of claim 1, further comprising:

identifying a set of interfering lifetimes; and

spilling a corresponding set of values associated with the interfering lifetimes prior to allocating rotating registers.

7. The method of claim 1, wherein the scalar register allocator selects a rotating register for assigning a scalar lifetime variable value.

8. The method of claim 7, wherein the scalar register allocator selects the rotating register for assignment responsive to the rotating register usage information.

9. A computer-readable medium having a program for improving register allocation in an optimizing compiler, the program comprising:

logic configured to receive a representation of a source code program loop;

logic configured to identify live ranges of variables used within the source code program loop that exceed an initiation interval of the source code program loop;

logic configured to allocate rotating registers for each of the variables;

logic configured to assign values for each of the variables that are initiated within the source code program loop; and

logic configured to communicate with a scalar register allocator responsive to the logic configured to allocate rotating registers and the logic configured to assign values.

10. The computer-readable medium of claim 9, further comprising:

logic configured to identify live ranges that overlap the source code program loop; and

logic configured to spill live ranges responsive to the logic configured to identify live ranges that overlap the source code program loop.

11. The computer-readable medium of claim 9, wherein the logic configured to receive receives a modulo schedule.

12. The computer-readable medium of claim 11, further comprising:

logic configured to identify a location in the schedule for spill code.

13. The computer-readable medium of claim 9, further comprising:

logic configured to recognize a pipeline processed intermediate representation of the source code; and

logic configured to minimize an amount of spill code generated within the loop of interest.

14. The computer-readable medium of claim 9, further comprising:

logic configured to recognize and reassign scalar lifetime values overwritten within the loop upon exiting the programming loop.

15. The computer-readable medium of claim 9, further comprising:

logic configured to select a rotating register for an assignment of a scalar lifetime variable value.

16. The computer-readable medium of claim 15, wherein the logic configured to select is responsive to logic configured to report rotating register usage information.

17. A compiler, comprising:

means for receiving a schedule representation of a source code loop;

means for identifying live ranges of variables within the schedule representation;

means for classifying the variables responsive to when each respective variable is defined;

means for managing a plurality of rotating registers responsive to the means for classifying; and

means for communicating rotating register usage information responsive to the means for managing.

18. The compiler of claim 17, further comprising:

means for recognizing interfering variables in the schedule; and

means for spilling the interfering variables to static registers outside the loop.

19. The compiler of claim 18, further comprising:

means for restoring the interfering variables outside the loop upon termination of the schedule.

20. The compiler of claim 17, further comprising:

means for applying variables with scalar lifetimes to rotating registers responsive to the means for communicating.

21. An optimizing compiler, comprising:

a translation engine configured to receive source code and generate an intermediate representation of a source code programming loop; and

a low-level instruction optimizer, the low-level instruction optimizer further comprising a scheduler and register allocator, the scheduler and register allocator comprising;

an initiation interval determiner configured to identify where in the source code each of a plurality of variables is identified and when variables are defined within a programming loop, in which of a plurality of programming loops each respective variable is defined;

a modulo scheduler configured to receive the intermediate representation and generate a schedule responsive to the source code programming loop;

a rotating register allocator configured to receive the schedule, allocate and assign rotating registers responsive to the schedule and initiation interval, and communicate a status of a set of rotating registers;

a static register allocator configured to receive the schedule, allocate and assign scalar variables to a set of scalar registers responsive to the initiation interval determiner and the status; and

a rotating register spiller configured to receive and store interfering variables in a memory.

22. The optimizing compiler of claim 21, wherein the scheduler and register allocator further comprises an interfering lifetime identifier configured to analyze the status and the set of scalar registers to identify candidate registers for a rotating register spill operation.

23. The optimizing compiler of claim 21, wherein the static register allocator further comprises a static register spiller configured to receive and store scalar variables to an allocated and unassigned rotating register.

24. The optimizing compiler of claim 21, wherein the scalar register allocator selects a rotating register for assigning a scalar lifetime variable value.

25. The optimizing compiler of claim 24, wherein the scalar register allocator selects the rotating register for assignment responsive to the rotating register usage information.

26. The optimizing compiler of claim 24, wherein the scalar register allocator is configured to recognize a pipeline processed intermediate representation of the source code.

27. The optimizing compiler of claim 26, wherein the scalar register allocator is configured to minimize an amount of spill code generated.