Etch stop layer system

• US 20040000268A1
• Filed: 06/25/2003
• Published: 01/01/2004
• Est. Priority Date: 04/10/1998
• Status: Active Grant

• Current Assignee: Charles Stark Draper Laboratory Incorporated
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Borenstein, Jeffrey T., Fitzgerald, Eugene A., Taraschi, Gianni, Wu, Kenneth C.
• Granted Patent: US 7,227,176 B2
• Time in Patent Office: Days
• US Class Current: 117/94
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN

Abstract

A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si_1-xGe_x alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. These solutions generally etch any silicon containing less than 7×10¹⁹ cm⁻³ of boron or undoped Si_1-xGe_x alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium. Furthermore, the nondegenerate doping in the Si_1-xGe_x alloy should not affect the etch-stop behavior. The etch-stop of the invention includes the use of a graded-composition buffer between the silicon substrate and the SiGe etch-stop material. Nominally, the buffer has a linearly-changing composition with respect to thickness, from pure silicon at the substrate/buffer interface to a composition of germanium, and dopant if also present, at the buffer/etch-stop interface which can still be etched at an appreciable rate. Here, there is a strategic jump in germanium and concentration from the buffer side of the interface to the etch-stop material, such that the etch-stop layer is considerably more resistant to the etchant. This process and layer structure allows for an entire range of new materials for microelectronics. The etch-stop capabilities introduce new novel processes and structures such as relaxed SiGe alloys on Si, SiO₂, and SiO₂/Si. Such materials are useful for future strained Si MOSFET devices and circuits.

Claims

1. A monocrystalline etch-stop layer system for use on a monocrystalline Si substrate, said system comprising a substantially relaxed graded layer of Si_1-xGe_x, and a uniform etch-stop layer of substantially relaxed Si_1-yGe_y.

2. The system of claim 1, wherein x<

0.20.

3. The system of claim 1, wherein y>

0.19.

4. The system of claim 1, wherein x<

0.20 and y>

0.19.

5. The system of claim 1, wherein said Si_1-yGe_y layer is bonded to a second substrate.

6. The system of claim 5, wherein said second substrate comprises Si.

7. The system of claim 5, wherein said second substrate comprises glass.

8. The system of claim 5., wherein said second substrate comprises quartz.

9. The system of claim 5, wherein said second substrate comprises a layer of SiO₂ on a second Si substrate.

10. The system of claim 5, wherein the first Si substrate and graded layer are substantially removed.

11. The system of claim 6, wherein the first Si substrate and graded layer are substantially removed.

12. The system of claim 7, wherein the first Si substrate and graded layer are substantially removed.

13. The system of claim 8, wherein the first Si substrate and graded layer are substantially removed.

14. The system of claim 9, wherein the first Si substrate and graded layer are substantially removed.

15. The system of claim 1, wherein a SiO₂ layer is deposited onto said Si_1-yGe_y layer.

16. The system of claim 15, wherein said SiO₂ layer is bonded to a second substrate.

17. The system of claim 16, wherein said second substrate comprises a layer of SiO₂ on a second Si substrate.

18. The system of claim 16, wherein said second substrate comprises a layer of SiO₂ on a glass substrate.

19. The system of claim 16, wherein said second substrate comprises a layer of SiO₂ on a quartz substrate.

20. The system of claim 16, wherein the first Si substrate and graded layer are substantially removed.

21. The system of claim 17, wherein the first Si substrate and graded layer are substantially removed.

22. The system of claim 18, wherein the first Si substrate and graded layer are substantially removed.

23. The system of claim 19, wherein the first Si substrate and graded layer are substantially removed.

24. The system of claim 10, wherein the surface is planarized.

25. The system of claim 11, wherein the surface is planarized.

26. The system of claim 12, wherein the surface is planarized.

27. The system of claim 13, wherein the surface is planarized.

28. The system of claim 14, wherein the surface is planarized.

29. The system of claim 20, wherein the surface is planarized.

30. The system of claim 21, wherein the surface is planarized.

31. The system of claim 22, wherein the surface is planarized.

32. The system of claim 23, wherein the surface is planarized.

33. A monocrystalline etch-stop layer system for use on a monocrystalline Si substrate, said system comprising a substantially relaxed graded layer of Si_1-xGe_xa uniform etch-stop layer of substantially relaxed Si_1-yGe_y;

and a strained Si_1-zGe_z layer.

34. The system of claim 0.33, wherein z<

y.

35. The system of claim 33, wherein y>

0.18.

36. The system of claim 33, wherein y>

0.18 and z<

y.

37. The system of claim 33, wherein y>

0.18 and z=0.

38. The system of claim 33, wherein said Si_1-xGe_x is bonded to a second substrate.

39. The system of claim 38, wherein said second substrate comprises Si.

40. The system of claim 38, wherein said second substrate comprises glass.

41. The system of claim 38, wherein said second substrate comprises quartz.

42. The system of claim 38, wherein said second substrate comprises a layer of SiO₂ on a second Si substrate.

43. The system of claim 38, wherein the first Si substrate and graded layer are substantially removed.

44. The system of claim 39, wherein the first Si substrate and graded layer are substantially removed.

45. The system of claim 40, wherein the first Si substrate and graded layer are substantially removed.

46. The system of claim 41, wherein the first Si substrate and graded layer are substantially removed.

47. The system of claim 42, wherein the first Si substrate and graded layer are substantially removed.

48. The structure in claim 33 in which a SiO₂ layer is deposited onto said Si_1-xGe_x layer.

49. The system of claim 48, wherein said SiO₂ layer is bonded to a second substrate.

50. The system of claim 49, wherein the second substrate comprises a layer of SiO₂ on a second Si substrate.

51. The system of claim 49, wherein the second substrate comprises a layer of SiO₂ on a glass substrate.

52. The system of claim 49, wherein the second substrate comprises a layer of SiO₂ on a quartz substrate.

53. The system of claim 49, wherein the first Si substrate and graded layer are substantially removed.

54. The system of claim 50, wherein the first Si substrate and graded layer are substantially removed.

55. The system of claim 51, wherein the first Si substrate and graded layer are substantially removed.

56. The system of claim 52, wherein the first Si substrate and graded layer are substantially removed.

57. A monocrystalline etch-stop layer system for use on a monocrystalline Si substrate, comprising a substantially relaxed graded layer of Si_1-xGe_x;

a uniform etch-stop layer of substantially relaxed Si_1-yGe_y;

a second etch-stop layer of strained Si_1-zGe_z; and

a substantially relaxed Si_1-wGe_w layer.

58. The system of claim 57, wherein y−

0.05<

w<

y+0.05.

59. The system of claim 57, wherein w=y.

60. The system of claim 57, wherein said Si_1-wGe_w is bonded to a second substrate.

61. The system of claim 60, wherein said second substrate comprises Si.

62. The system of claim 60, wherein said second substrate comprises glass.

63. The system of claim 60, wherein said second substrate comprises quartz.

64. The system of claim 60, wherein said second substrate comprises a layer of SiO₂ on a second Si substrate.

65. The system of claim 60, wherein the first Si substrate and graded layer are substantially removed.

66. The system of claim 61, wherein the first Si substrate and graded layer are substantially removed.

67. The system of claim 62, wherein the first Si substrate and graded layer are substantially removed.

68. The system of claim 63, wherein the first Si substrate and graded layer are substantially removed.

69. The system of claim 64, wherein the first Si substrate and graded layer are substantially removed.

70. The system of claim 57, wherein a SiO₂ layer is deposited onto said Si_1-wGe_w layer.

71. The system of claim 70, wherein said SiO₂ layer is bonded to a second substrate.

72. The system of claim 70, wherein the second substrate comprises a layer of SiO₂ on a second Si substrate.

73. The system of claim 70, wherein the second substrate comprises a layer of SiO₂ on a glass substrate.

74. The system of claim 70, wherein the second substrate comprises a layer of SiO₂ on a quartz substrate.

75. The system of claim 70, wherein the first Si substrate and graded layer are substantially removed.

76. The system of claim 71, wherein the first Si substrate and graded layer are substantially removed.

77. The system of claim 72, wherein the first Si substrate and graded layer are substantially removed.

78. The system of claim 73, wherein the first Si substrate and graded layer are substantially removed.

79. The system of claim 74, wherein the first Si substrate and graded layer are substantially removed.

80. A method of integrating a device or layer comprising:

depositing a substantially relaxed graded layer of Si_1-xGe_x;

on a Si substrate;

depositing a uniform etch-stop layer of substantially relaxed Si_1-yGe_y on said graded buffer; and

etching portions of said substrate and said graded buffer in order to release said etch-stop layer.

81. The method of claim 80, wherein x<

0.20.

82. The method of claim 80, wherein y>

0.19.

83. The method of claim 80, wherein x<

0.20 and y>

0.19.

84. The method of claim 80, wherein the etchant used to release the etch-stop layer is KOH.

85. The method of claim 80, wherein the etchant used to release the etch-stop layer is TMAH.

86. The method of claim. 80, wherein the etchant used to release the etch-stop layer is EDP.

87. The method of claim 80, wherein the etch-stop is released and the etch-stop layer is planarized.

88. The method of claim 87, wherein the method of planarization is chemical-mechanical polishing (CMP).

89. A method of integrating a device or layer comprising:

depositing a substantially relaxed graded layer of Si_1-xGe_x on a Si substrate;

depositing a uniform first etch-stop layer of substantially relaxed Si_1-yGe_y on said graded buffer;

depositing a second etch-stop layer of strained Si_1-xGe_x;

depositing a substantially relaxed Si_1-wGe_w layer;

etching portions of said substrate and said graded buffer in order to release said first etch-stop layer; and

etching portions of said residual graded buffer in order to release the second etch-stop Si_1-zGe_z layer.

90. The method of claim 89, wherein the etchant used to release the second etch-stop layer comprises an oxidant and an oxide stripping agent.

91. The method of claim 90, wherein the oxidant oxidizes Ge much more rapidly than Si.

92. The method of claim 90, wherein the oxidant comprises H₂O₂.

93. The method of claim 90, wherein the stripping agent comprises HF.

94. The method of claim 90, wherein the oxidant comprises H₂O₂ and the stripping agent comprises HF.

95. The method of claim 94, wherein the diluting agent comprises CH₃COOH.

96. The method of claim 95, wherein the ratio of chemicals in the etchant are (1:

2;

3) for (HF;

H₂O₂;

CH₃COOH).

97. The method of claim 89, wherein wet oxidation is used to selectively oxidize the Si_1-xGe_x;

and Si, thereby acting as an etch-stop with respect to Si_1-yGe_y.

98. The method of claim 97, wherein the wet oxidation temperature is <

750 degrees Celsius.

99. The method of claim 97, wherein the oxidized layers are removed by an HF and water solution.

100. The method of claim 98, wherein the oxidized layers are removed by an HF solution.

101. The method of claim 90, wherein the Si_1-zGe_z layer is subsequently removed using a selective etchant with respect to the Si_1-wGe_w layer.

102. The method of claim 91, wherein the Si_1-zGe_z layer is subsequently removed using a selective etchant with respect to the Si_1-wGe_w layer.

103. The method of claim 92, wherein the Si_1-zGe_z layer is subsequently removed using a selective etchant with respect to the Si_1-wGe_w layer.

104. The method of claim 93, wherein the Si_1-zGe_z layer is subsequently removed using a selective etchant with respect to the Si_wGe_w layer.

105. The method of claim 94, wherein the Si_1-zGe_z, layer is subsequently removed using a selective etchant with respect to the Si_1-wGe_w layer.

106. The method of claim 95, wherein the Si_1-zGe_z layer is subsequently removed using a selective etchant with respect to the Si_1-wGe_w layer.

107. The method of claim 96, wherein the Si_1-zGe_z, layer is subsequently removed using a selective etchant with respect to the Si_1-wGe_w layer.

108. The method of claim 97, wherein the Si_1-zGe_z layer is subsequently removed using a selective etchant with respect to the Si_1-wGe_w layer.

109. The method of claim 98, wherein the Si_1-zGe_z layer is subsequently removed using a selective etchant with respect to the Si_1-wGe_w layer.

110. The method of claim 99, wherein the Si_1-zGe_z layer is subsequently removed using a selective etchant with respect to the Si_1-wGe_w layer.

111. The method of claim 100, wherein the Si_1-zGe_z layer is subsequently removed using a selective etchant with respect to the Si_1-wGe_w layer.

112. (New) A semiconductor structure comprising:

a layer structure including a uniform etch-stop layer,

wherein said uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm^3.

113. (New) The semiconductor structure of claim 112, wherein the uniform etch-stop layer is substantially relaxed.

114. (New) The semiconductor structure of claim 113, wherein the uniform etch-stop layer comprises Si_1-yGe_y.

115. (New) The semiconductor structure of claim 114, wherein y>

0.19.

116. (New) The semiconductor structure of claim 113, wherein the uniform etch-stop layer comprises a silicon dioxide layer.

117. (New) The semiconductor structure of claim 113, wherein a surface of the uniform etch-stop layer is planarized.

118. (New) The semiconductor structure of claim 112, wherein the layer structure comprises a strained layer disposed over the uniform etch stop layer.

119. (New) The semiconductor structure of claim 118, wherein the strained layer comprises Si_1-zGe_z and 0≦

z<

1.

120. (New) The semiconductor structure of claim 118, further comprising:

an insulator layer disposed over the layer structure.

121. (New) The semiconductor structure of claim 112, further comprising:

a handle wafer,

wherein the layer structure is bonded to the handle wafer.

122. (New) The structure of claim 121, wherein the handle wafer comprises an insulator.

123. (New) The semiconductor structure of claim 121, wherein the handle wafer comprises a material selected from the group consisting of silicon, glass, quartz, and silicon dioxide.

124. (New) The semiconductor structure of claim 123, wherein the handle wafer comprises a silicon dioxide layer.

125. (New) The semiconductor structure of claim 112, wherein the layer structure comprises a substantially relaxed layer.

126. (New) The semiconductor structure of claim 125, wherein the relaxed layer is graded.

127. (New) The semiconductor structure of claim 126, wherein the relaxed layer comprises Si_1-xGe_x.

128. (New) The semiconductor structure of claim 127, wherein x<

0.2.

129. (New) The semiconductor structure of claim 128, wherein the uniform etch-stop layer comprises substantially relaxed Si_1-yGe_y and y>

0.19.

130. (New) The semiconductor structure of claim 125, wherein the substantially relaxed layer is disposed over the uniform etch-stop layer.

131. (New) The semiconductor structure of claim 130, further comprising:

a semiconductor substrate disposed over the relaxed layer.

132. (New) The semiconductor structure of claim 125, wherein the substantially relaxed layer is disposed under the uniform etch-stop layer.

133. (New) The semiconductor structure of claim 132, wherein the layer structure comprises a first strained layer disposed over the uniform etch-stop layer.

134. (New) The semiconductor structure of claim 132, wherein the first strained layer comprises Si_1-zGe_z and 0≦

z<

1.

135. (New) A semiconductor structure, comprising:

a layer structure including a strained Si_1-zGe_z layer, and

a handle wafer comprising an insulator, the layer structure being bonded to the handle wafer,

wherein 0<

z<

1.

136. (New) The semiconductor structure of claim 135, wherein z=0.

137. (New) The semiconductor structure of claim 135, wherein the layer structure includes a substantially relaxed uniform etch-stop layer, the strained Si_1-zGe_z layer is disposed over the uniform etch-stop layer, 0≦

z<

1, and the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

138. (New) The semiconductor structure of claim 137, wherein the etch-stop layer comprises substantially relaxed Si_1-yGe_y.

139. (New) The semiconductor structure of claim 137, wherein the layer structure comprises a substantially relaxed layer and the uniform etch-stop layer is disposed over the substantially relaxed layer.

140. (New) The semiconductor structure of claim 139, wherein the substantially relaxed layer comprises graded Si_1-xGe_x.

141. (New) The structure of claim 139, further comprising:

an insulator layer disposed over the layer structure.

142. (New) The semiconductor structure of claim 139, wherein the layer structure comprises a substantially relaxed graded layer disposed over the substantially relaxed layer.

143. (New) The semiconductor structure of claim 142, wherein the substantially relaxed graded layer comprises Si_1-xGe_x.

144. (New) A semiconductor structure, comprising:

a layer structure including;

a uniform etch-stop layer; and

a strained layer disposed over the uniform etch-stop layer, and

an insulator layer disposed over the layer structure,

wherein the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

145. (New) The semiconductor structure of claim 144, wherein the etch-stop layer comprises substantially relaxed Si_1-yGe_y.

146. (New) The semiconductor structure of claim 144, wherein the strained layer comprises Si_1-zGe_z and 0≦

z<

1.

147. (New) A semiconductor structure, comprising:

an etch-stop layer; and

a substantially relaxed layer disposed over the etch-stop layer.

148. (New) The semiconductor structure of claim 147, wherein the etch-stop layer comprises strained Si_1-zGe_z, and 0≦

z<

1.

149. (New) The semiconductor structure of claim 148, wherein z=0.

150. (New) The semiconductor structure of claim 147, wherein the substantially relaxed layer comprises Si_1-wGe_w.

151. (New) A semiconductor structure, comprising:

a first uniform etch-stop layer;

a second etch-stop layer disposed over the uniform etch-stop layer; and

a substantially relaxed layer disposed over the second etch-stop layer,

wherein the first uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm^3.

152. (New) The semiconductor structure of claim 151, wherein the first uniform etch-stop layer comprises substantially relaxed Si_1-yGe_y.

153. (New) The semiconductor structure of claim 151, wherein the second etch-stop layer comprises strained Si_1-zGe_z.

154. (New) The structure of claim 153, wherein 0≦

z<

1.

155. (New) The semiconductor structure of claim 154, wherein z=0.

156. (New) The semiconductor structure of claim 151, wherein the substantially relaxed layer comprises Si_1-wGe_w.

157. (New) The semiconductor structure of claim 151, further comprising:

a handle wafer comprising an insulator,

wherein the substantially relaxed layer is bonded to the handle wafer.

158. (New) The semiconductor structure of claim 157, wherein the handle wafer comprises a material selected from the group consisting of silicon, glass, quartz, and silicon dioxide.

159. (New) The semiconductor structure of claim 157, further comprising:

an insulator layer disposed over the strained layer.

160. (New) The semiconductor structure of claim 151, further comprising:

a substantially relaxed graded layer,

wherein the first uniform etch-stop layer is disposed over the graded layer.

161. (New) The semiconductor structure of claim 160, wherein the substantially relaxed graded layer comprises Si_1-xGe_x.

162. (New) The semiconductor structure of claim 160, further comprising:

a first substrate,

wherein the substantially relaxed graded layer is disposed on the first substrate.

163. (New) A method for forming a semiconductor structure, the method comprising:

forming a uniform etch-stop layer;

providing a handle wafer; and

bonding the uniform etch-stop layer to the handle wafer,

wherein said uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

164. (New) The method of claim 163, wherein the uniform etch-stop layer comprises substantially relaxed Si_1-yGe_y.

165. (New) The method of claim 163, further comprising:

planarizing a surface of the uniform etch-stop layer prior to bonding.

166. (New) The method of claim 163, further comprising:

forming a substantially relaxed graded layer before forming the uniform etch-stop layer, wherein the uniform etch-stop layer is formed over the substantially relaxed graded layer.

167. (New) The method of claim 166, wherein the relaxed graded layer comprises Si_1-xGe_x.

168. (New) The method of claim 166, further comprising:

releasing the etch-stop layer by removing at least a portion of the graded layer.

169. (New) The method of claim 166, wherein releasing the etch-stop layer comprises a wet etch.

170. (New) The method of claim 166, further comprising:

providing a semiconductor substrate,

wherein the substantially relaxed graded layer is formed over the semiconductor substrate.

171. (New) A method for forming a semiconductor structure, the method comprising:

providing a first substrate; and

forming a layer structure over the first substrate by;

forming a uniform etch-stop layer over the first substrate; and

forming a strained layer over the uniform etch-stop layer,

wherein the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

172. (New) The method of claim 171, wherein the etch-stop layer comprises substantially relaxed Si_1-yGe_y.

173. (New) The method of claim 171, wherein the strained layer comprises Si_1-zGe_z and 0≦

z<

1.

174. (New) The method of claim 171, further comprising:

providing a second substrate comprising an insulator; and

bonding the layer structure to the second substrate.

175. (New) The method of claim 174, wherein the second substrate comprises a material selected from the group consisting of silicon, glass, quartz, and silicon dioxide.

176. (New) The method of claim 171, further comprising:

forming an insulator layer over the strained layer.

177. (New) The method of claim 171, further comprising:

releasing the strained layer by removing at least a portion of the uniform etch-stop layer.

178. (New) The method of claim 177, wherein releasing the strained layer comprises a wet etch.

179. (New) The method of claim 171, wherein forming the layer structure comprises forming a substantially relaxed graded layer and the uniform etch-stop layer is formed over the graded layer.

180. (New) The method of claim 179, wherein the graded layer comprises Si_1-xGe_x.

181. (New) The method of claim 179, further comprising:

releasing the strained layer by removing at least a portion of the graded layer and at least a portion of the uniform etch-stop layer.

182. (New) The method of claim 181, wherein releasing the strained layer comprises a wet etch.

183. (New) A method for forming a semiconductor structure, the method comprising:

forming a layer structure by forming a strained Si_1-zGe_z layer, and bonding the layer structure to a handle wafer comprising an insulator, wherein 0≦

z<

1.

184. (New) The method of claim 183, wherein z=0.

185. (New) The method of claim 183, wherein forming the layer structure comprises forming a uniform etch-stop layer, the strained Si_1-xGe_x layer is formed over the uniform etch-stop layer, and the uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

186. (New) The method of claim 185, wherein the uniform etch-stop layer comprises substantially relaxed Si_1-yGe_y.

187. (New) The method of claim 185, further comprising:

forming an insulator layer over the layer structure.

188. (New) The method of claim 185, further comprising:

releasing the strained layer by removing at least a portion of the uniform etch-stop layer.

189. (New) The method of claim 188, wherein releasing the strained layer comprises a wet etch.

190. (New) The method of claim 185, wherein forming the layer structure comprises forming a substantially relaxed graded layer, and the uniform etch-stop layer is formed over the substantially graded layer.

191. (New) The method of claim 190, wherein the relaxed graded layer comprises Si_1-xGe_x.

192. (New) The method of claim 190, further comprising:

releasing the strained layer by removing at least a portion of the graded layer and at least a portion of the uniform etch-stop layer.

193. (New) The method of claim 192, wherein releasing the strained layer comprises a wet etch.

194. (New) The method of claim 190, further comprising:

forming an insulator layer over the layer structure.

195. (New) The method of claim 190, further comprising:

providing a substrate,

wherein the layer structure is formed over the substrate.

196. (New) The method of claim 195, further comprising:

releasing the strained layer by removing at least a portion of the substrate, at least a portion of the graded layer, and at least a portion of the uniform etch-stop layer.

197. (New) The method of claim 196, wherein releasing the strained layer comprises a wet etch.

198. (New) A method for forming a semiconductor structure, the method comprising:

forming a strained etch-stop layer; and

forming a substantially relaxed Si_1-wGe_w layer over the etch-stop layer.

199. (New) The method of claim 198, wherein the etch-stop layer comprises Si_1-zGe_z and wherein 0≦

z<

1.

200. (New) The method of claim 199, wherein z=0.

201. (New) A method for forming a semiconductor structure, the method comprising:

forming a first uniform etch-stop layer;

forming a second etch-stop layer over the uniform etch-stop layer; and

forming a substantially relaxed layer over the second etch-stop layer, wherein the first uniform etch-stop layer has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

202. (New) The method of claim 201, wherein the first etch-stop layer comprises substantially relaxed Si_1-yGe_y.

203. (New) The method of claim 201, wherein the second etch-stop layer comprises strained Si_1-zGe_z and 0≦

z<

1.

204. (New) The method of claim 203, wherein z=O.

205. (New) The method of claim 201, wherein the substantially relaxed layer comprises Si_1-wGe_w.

206. (New) The method of claim 201, further comprising:

bonding the substantially relaxed layer to a substrate comprising an insulator.

207. (New) The method of claim 206, wherein the substrate comprises a material selected from the group consisting of silicon, glass, quartz, and silicon dioxide.

208. (New) The method of claim 206, further comprising:

releasing the second etch-stop layer by removing at least a portion of the first etch-stop layer.

209. (New) The method of claim 208, wherein releasing the second etch-stop layer comprises a wet etch.

210. (New) The method of claim 208, further comprising:

releasing the substantially relaxed layer by removing at least a portion of the second etch-stop layer.

211. (New) The method of claim 208, wherein releasing the substantially relaxed layer comprises a wet etch.

212. (New) The method of claim 201, further comprising:

forming a substantially relaxed graded layer, wherein the first uniform etch-stop layer is formed on the graded layer.

213. (New) The method of claim 212, wherein the substantially relaxed graded layer comprises Si_1-xGe_x.

214. (New) The method of claim 212, further comprising:

bonding the substantially relaxed layer to a substrate comprising an insulator.

215. (New) The method of claim 212, further comprising:

releasing the first etch-stop layer by removing at least a portion of the relaxed graded layer.

216. (New) The method of claim 215, wherein releasing the first etch-stop layer comprises a wet etch.

217. (New) The method of claim 215, further comprising:

releasing the second etch-stop layer by removing at least a portion of the first etch-stop layer.

218. (New) The method of claim 215, wherein releasing the second etch-stop layer comprises a wet etch.

219. (New) The method of claim 217, further comprising:

releasing the relaxed layer by removing at least a portion of the second etch-stop layer.

220. (New) The method of claim 219, wherein releasing the relaxed layer comprises a wet etch.

221. (New) The method of claim 201, further comprising:

providing a first substrate; and

forming a layer structure over the first substrate by;

forming a substantially relaxed graded layer over the first substrate;

wherein the first uniform etch-stop layer is formed over the graded layer, and the layer structure comprises the substantially relaxed graded layer, the first uniform etch-stop layer, the second etch-stop layer, and the substantially relaxed layer.

222. (New) The method of claim 221, wherein the substantially relaxed graded layer comprises Si_1-xGe_x.

223. (New) The method of claim 221, wherein the first uniform etch-stop layer comprises substantially relaxed Si_1-yGe_y, the second etch-stop layer comprises strained Si_1-zGe_z0≦

z<

1, and the substantially relaxed layer comprises Si_1-wGe_w.

224. (New) The method of claim 221, further comprising:

bonding the layer structure to a second substrate including an insulator.

225. (New) The method of claim 224, wherein the second substrate comprises a material selected from the group consisting of silicon, glass, quartz, and silicon dioxide.

226. (New) The method of claim 221, the method further comprising:

releasing the first etch-stop layer by removing at least a portion of the first substrate and at least a portion of the graded layer; and

releasing the second etch-stop layer by removing at least a portion of the first etch-stop layer.

227. (New) The method of claim 226, further comprising:

bonding the layer structure to a second substrate prior to releasing the first etch-stop layer.

228. (New) The method of claim 226, further comprising:

releasing at least a portion of the relaxed layer by removing at least a portion of the second etch-stop layer.

229. (New) A method for forming a semiconductor structure, the method comprising:

providing a first substrate;

forming a layer structure on the first substrate by;

forming a substantially relaxed graded layer on the first substrate; and

forming a uniform etch-stop layer on the graded layer; and

releasing the etch-stop layer by removing at least a portion of the substrate and at least a portion of the graded layer,