Methods for fabricating three-dimensional all organic interconnect structures

• US 20040000425A1
• Filed: 03/28/2003
• Published: 01/01/2004
• Est. Priority Date: 06/26/2002
• Status: Active Grant

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Sundaram, Venkatesh, Swaminathan, Madhavan, Dalmia, Sidharth, White, George E.
• Granted Patent: US 7,260,890 B2
• Time in Patent Office: Days
• US Class Current: 174/250
• CPC Class Codes: B32B 37/00 Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/00 : Printed circuits
• CPC Class Codes: H05K 1/162 : incorporating printed capacitors
• CPC Class Codes: H05K 1/167 : incorporating printed resistors
• CPC Class Codes: H05K 2201/0129 : Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
• CPC Class Codes: H05K 2201/0141 : Liquid crystal polymer [LCP]
• CPC Class Codes: H05K 2201/0209 : Inorganic, non-metallic particles
• CPC Class Codes: H05K 3/4617 : characterized by laminating only or mainly similar single-sided circuit boards
• CPC Class Codes: H05K 3/4632 : laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
• CPC Class Codes: H05K 3/4688 : Composite multilayer circuits, i.e. comprising insulating layers having different properties having a special base or central core H05K3/4602
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49149 : by metal fusion bonding
• CPC Class Codes: Y10T 29/49158 : with molding of insulated base

Abstract

The present invention comprises methods for making three-dimensional (3-D) liquid crystalline polymer (LCP) interconnect structures using a high temperature singe sided liquid crystalline polymer, and low temperature single sided liquid crystalline polymer, whereas both the high temperature LCP and the low temperature LCP are drilled using a laser or mechanical drill or mechanically punch to form a z-axis connection. The single sided Conductive layer is used as a bus layer to form z axis conductive stud conductive stud within the high temperature and low temperature LCP, followed by deposition of a metallic capping layer of the stud that serves as the bonding metal between the conductive interconnects to form the z-axis electrical connection. High temperature and low temperature LCP circuit layers are etched or built up to form circuit patterns and subsequently bonded together to form final 3-D multilayer circuit pattern whereas the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond, whereas, metal to metal bonding occurs with high temperature metal capping layer bonding to conductive metal layer. The resultant structure is then packaged using two metallized organic cores that are laminated onto either side of the device using a low temperature adhesive with similar electrical properties and subsequently metallized to form the input output terminals and EM shielding.

Claims

1. A method of fabricating 3-D multilayer interconnect structures, comprising;

providing a first single sided circuitized layer of a first melting point having a first conductive layer;

providing a second single sided circuitized layer of a second melting point including at least one metal filled z-axis via connection stud;

capping the z-axis stud of the second organic layer with a high temperature bonding material; and

bonding the low temperature organic layer to the high temperature organic layer;

wherein the first organic layer forms a fusion bond with the second organic layer, and the cap on the second organic layer forms a metal to metal bond with the conductive layer first organic layer.

2. The method of claim 1, wherein the conductive layer comprises at least one of copper, aluminum, gold, nickel, iron, silver, zinc, chromium and a combination thereof.

3. The method of claim 1, wherein at least one conductive layer on one of the low temperature and high temperature organic layers serves as a bus layer prior to the z-axis via stud formation.

4. The method of claim 1, wherein the first melting point is less than the second melting point.

5. The method of claim 1, wherein the first melting point is greater than the second melting point.

6. The method of claim 1, wherein the cap on the vias of the second organic LCP layer is a metallic solder of a binary alloy that melts above a fusion point of the first and second organic layers.

7. The method of claim 1, wherein the first conductive layer has a thickness from approximately 0.5 microns to 200 microns.

8. The method of claim 1, wherein the first and second organic layers are laminated together in a stack to form a three-dimensional (3-D) circuit.

9. The method of claim 8, wherein the 3-D circuit is a flexible circuit.

10. The method of claim 8, wherein the 3-D circuit is a rigid circuit.

11. The method of claim 8, wherein the coefficient of thermal expansion of the completed 3-D circuit in the x and y directions are substantially matched.

12. The method of claim 8, wherein the coefficient of thermal expansion of the first and second organic layers is between 2 and 20 ppm/°

C.

13. The method of claim 1, wherein the second organic layer is sufficiently filled with high k dielectric constant particles to achieve a suitable high k film for high value capacitors and resonator structures.

14. The method of claim 1, wherein the second organic layer includes a thin film of high k dielectric constant material.

15. The method of claim 1, wherein the second organic layer is sufficiently filled with resistive particles and circuitized to form a resistor or a resistor network.

16. The method of claim 1, wherein the second organic layer includes a thin film of resistive material.

17. The method of claim 1, further comprising an expansion matched core that is bonded to one of the first or second organic layers to provide expansion matching to one of an organic, ceramic and metal substrates.

18. The method of claim 1, wherein the expansion matched core is metallic, and performs thermal and electrical functions.

19. A multilayer liquid crystalline polymer circuit;

comprising

low temperature liquid crystalline polymer layer (LCP) having a single circuitized surface;

high temperature liquid crystalline polymer layer having a single circuitized surface;

at least one z-axis interconnect structure interconnecting the circuitized surfaces of the low temperature and high temperature LCP layers.

20. The circuit of claim 19, wherein at least one of the low temperature and high temperature LCP layers comprises at least one of high k particles and resistive particles.

21. The circuit of claim 19, wherein one of the low temperature and high temperature LCP layers includes a z-axis via aligned in the z-axis with one of the z-axis interconnect structure.