Method and apparatus for implementing alterations on multiple concurrent frames

• US 20040001484A1
• Filed: 06/27/2002
• Published: 01/01/2004
• Est. Priority Date: 06/27/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ozguner, Tolga
• Granted Patent: US 7,239,635 B2
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

A method and apparatus are provided for implementing frame header alterations on multiple concurrent frames. Each of a plurality of frame data alteration engines includes a pair of a command decoder and an associated data aligner. A command buffer arbiter sequentially receives frame alteration commands and sequentially selects one of the frame data alteration engines for the sequentially received frame alteration commands. Each command decoder receives and decodes frame alteration commands and provides frame alignment commands and alteration instructions and each associated data aligner receives frame data and selectively latches data bytes of the received frame data responsive to the frame alignment commands and sequentially provides an aligned frame data output of a predefined number of bytes. An alteration engine receives sequentially provided aligned frame data output and alteration instructions from a selected one the plurality of frame data alteration engines and provides sequential altered frame data responsive to the received alteration instructions.

Claims

1. Apparatus for implementing frame header alterations on multiple concurrent frames comprising:

a plurality of frame data alteration engines, each said frame data alteration engine including a pair of a command decoder and an associated data aligner;

a command buffer arbiter sequentially receiving frame alteration commands coupled to said plurality of frame data alteration engines sequentially selecting one of said frame data alteration engines for said received frame alteration commands;

each said command decoder receiving and decoding frame alteration commands and providing frame alignment commands and alteration instructions; and

each said associated data aligner receiving frame data and coupled to said associated command decoder receiving said frame alignment commands;

each said associated data aligner selectively latching data bytes of said received frame data responsive to said frame alignment commands and sequentially providing an aligned frame data output of said predefined number of bytes; and

an alteration engine coupled to said plurality of frame data alteration engines receiving said sequentially provided aligned frame data output and said alteration instructions from a selected frame data alteration engine and providing sequential altered frame data responsive to said received alteration instructions.

2. Apparatus for implementing frame header alterations on multiple concurrent frames as recited in claim 1 includes a mode control signal applied to said command buffer arbiter;

and wherein said command buffer arbiter is responsive to said mode control signal for sequentially selecting said one of said frame data alteration engines for said sequentially received frame alteration commands.

3. Apparatus for implementing frame header alterations on multiple concurrent frames as recited in claim 2 wherein said mode control signal is a full-bus mode control signal and wherein said command buffer arbiter is responsive to said full-bus mode control mode control signal for sequentially selecting a first available one of said frame data alteration engines for said sequentially received frame alteration commands.

4. Apparatus for implementing frame header alterations on multiple concurrent frames as recited in claim 2 wherein said mode control signal is a full-bus mode control signal and wherein said command buffer arbiter is responsive to said full-bus mode control mode control signal for sequentially selecting each of said frame data alteration engines in a predefined order for said sequentially received frame alteration commands.

5. Apparatus for implementing frame header alterations on multiple concurrent frames as recited in claim 2 wherein said mode control signal is a split-bus mode control signal and wherein each said sequentially received frame alteration commands include one of a plurality of destinations;

and wherein said command buffer arbiter responsive to said split-bus mode control mode control signal for sequentially selecting a designated one of said frame data alteration engines for each said destination for said sequentially received frame alteration commands.

6. Apparatus for implementing frame header alterations on multiple concurrent frames as recited in claim 5 wherein one destination is allocated use of multiple frame data alteration engines and wherein said command buffer arbiter for sequentially selecting a first available one of said frame data alteration engines for said one destination for said sequentially received frame alteration commands.

7. Apparatus for implementing frame header alterations on multiple concurrent frames as recited in claim 1 includes a packet buffer storing said frame data and a packet buffer arbiter coupled to said packet buffer sequentially receiving frame data and coupled to said plurality of frame data alteration engines sequentially selecting one of said frame data alteration engines for said sequentially received frame data.

8. Apparatus for implementing frame header alterations on multiple concurrent frames as recited in claim 7 includes a mode control signal applied to said command buffer arbiter;

and wherein said packet buffer arbiter is responsive to said mode control signal for sequentially selecting said one of said frame data alteration engines for said sequentially received frame data.

9. Apparatus for implementing frame header alterations on multiple concurrent frames as recited in claim 1 includes an aligned data and alteration instructions arbiter coupled between said alteration engine and said plurality of frame data alteration engines for selecting said aligned frame data output and said alteration instructions from one of said frame data alteration engines.

10. Apparatus for implementing frame header alterations on multiple concurrent frames as recited in claim 9 includes a mode control signal applied to said aligned data and alteration instructions arbiter;

and wherein said aligned data and alteration instructions arbiter is responsive to said mode control signal for sequentially selecting said aligned frame data output and said alteration instructions from one of said frame data alteration engines.

11. Apparatus for implementing frame header alterations on multiple concurrent frames as recited in claim 1 wherein said alteration engine includes first stage byte-wide alteration engines and second stage byte-wide alteration engines.

12. A method for implementing frame header alterations on multiple concurrent frames in a network processor including a plurality of distributed pico processor units (DPPUs) generating frame alteration commands coupled to a frame alteration unit, said method comprising the steps of:

providing a plurality of frame data alteration engines, each said frame data alteration engine including a pair of a command decoder and an associated data aligner;

sequentially selecting one of said frame data alteration engines for said sequentially received frame alteration commands;

utilizing each said command decoder and said associated data aligner, for receiving and decoding frame alteration commands and receiving frame data and sequentially providing alteration instructions and an aligned frame data output of said predefined number of bytes; and

sequentially selecting one of said frame data alteration engines for applying said predetermined number of bytes of aligned frame data together with said alteration instructions to an alteration engine and providing sequential altered frame data responsive to said received alteration instructions.

13. A method for implementing frame header alterations on multiple concurrent frames as recited in claim 12 wherein the steps of sequentially selecting one of said frame data alteration engines for said sequentially received frame alteration commands includes the steps of identifying a mode of the frame alteration unit.

14. A method for implementing frame header alterations on multiple concurrent frames as recited in claim 13 includes the steps responsive to identifying a full-bus mode, sequentially selecting a first available one of said frame data alteration engines for said sequentially received frame alteration commands.

15. A method for implementing frame header alterations on multiple concurrent frames as recited in claim 13 includes the steps responsive to identifying a full-bus mode, sequentially selecting each of said frame data alteration engines in a predefined order for said sequentially received frame alteration commands.

16. A method for implementing frame header alterations on multiple concurrent frames as recited in claim 13 wherein each said sequentially received frame alteration commands include one of a plurality of destinations;

includes the steps responsive to identifying a split-bus mode, sequentially selecting a designated one of said frame data alteration engines for each said destination for said sequentially received frame alteration commands.

17. A method for implementing frame header alterations on multiple concurrent frames as recited in claim 16 includes the steps of allocating one destination use of multiple frame data alteration engines and sequentially selecting a first available one of said frame data alteration engines for said one destination for said sequentially received frame alteration commands.

18. A method for implementing frame header alterations on multiple concurrent frames as recited in claim 13 includes the steps of providing an aligned data and alteration instructions arbiter coupled between said alteration engine and said plurality of frame data alteration engines, utilizing said aligned data and alteration instructions arbiter for selecting said aligned frame data output and said alteration instructions from one of said frame data alteration engines responsive to identifying said mode of the frame alteration unit.