Apparatus and method for arbitrating among equal priority requests

• US 20040001503A1
• Filed: 06/28/2002
• Published: 01/01/2004
• Est. Priority Date: 06/28/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Manter, Venitha L.
• Granted Patent: US 7,200,151 B2
• Time in Patent Office: Days
• US Class Current: 370/462
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/252 Store and forward routing
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3018 Input queuing

Abstract

A switch for use with an InfiniBand network having a management port adapted to arbitrate among equal priority signals requesting attention from ports on the switch. In particular, the management port included three registers that are used to arbitrate between the requests. The first register stores an indication of each type of signal from each port issuing the signal. The second register to indicate which single type of signal from which port has the priority to be handled next. The third register that indicates which signal is to be handled next or is currently being handled.

Claims

1. A switch for use with an InfiniBand network, the switch comprising:

a crossbar that redirects packet based data based on a forwarding table;

at least one port that receives data from a network and selectively transfers that data to the crossbar; and

a management port that receives requests to generate trap packets, the management port including three registers that are used to arbitrate between the requests.

2. A switch, as set forth in claim 1, wherein the three registers comprise:

a first register to store an indication of the type of request and the port issuing the request;

a second register to indicate which request has the priority to be handled next; and

a third register that indicates which request is to be handled next.

3. A switch, as set forth in claim 2, wherein the third register contains the logical AND of the first register and the second register.

4. A switch, as set forth in claim 2, wherein the second register is a one-hot shift register.

5. A switch as set forth in claim 1, wherein the at least one port comprises a plurality of ports.

6. A switch, as set forth in claim 5, wherein each port can issue requests for attention and wherein the three registers comprise:

a first register having at least as many bits as there are ports, each bit being associated with a port;

a second register having the at least as many bits as there are ports and configured as a one-hot shift register in which the hot bit indicates the port that currently has priority; and

a third register containing the logical AND of the first and second registers that indicates which request is to be handled next.

7. A switch, as set forth in claim 6, wherein the management port handles a request by transmitting a request to the port for information on the circumstances leading to the request.

8. A switch, as set forth in claim 7, wherein each port can respond with a plurality of indications regarding the circumstances leading to the request, and wherein the three registers comprise:

a first register having at least n bits where n is the number of ports times the number of indications;

a second register having at least n bits and configured as a one-hot shift register in which the hot bit indicates the indication that currently has priority; and

a third register containing the logical AND of the first and second registers that indicates which indication is to be handled next.

9. A switch, as set forth in claim 8, wherein the management port handles the indication by creating a trap packet based on the indication.

10. A switch, as set forth in claim 7 wherein each port can respond with a plurality of indications regarding the circumstances leading to the request, wherein the management port can issue a plurality of indications, and wherein the three registers comprise:

a first register having at least n bits where n is the number of ports times the number of indications that can be issued by each port plus the number of indications that can be issued by the management port;

a second register having at least n bits and configured as a one-hot shift register in which the hot bit indicates the indication that currently has priority; and

a third register containing the logical AND of the first and second registers that indicates which indication is to be handled next.

11. A switch, as set forth in claim 10, wherein the management port handles the indications from the ports by creating a trap packet and handles the indications from the management port by requesting further information from the management port.

12. A method of arbitrating among equal priority requests from a plurality of ports in an InfiniBand switch, the method comprising:

storing an indication of a port issuing the request;

cycling a pointer though each port; and

when the pointer points to a port for which an indication has been stored, handling the request from that port.

13. A method, as set forth in claim 12, wherein the indication for a port is cleared when the request has been handled.

14. A method, as set forth in claim 12, wherein the step of storing comprises setting a bit corresponding to the port that issued the request in a first register that has at least one bit per port.

15. A method, as set forth in claim 14, wherein the step of cycling comprises shifting a bit through a second register having at least one bit per port.

16. A method, as set forth in claim 15, further comprising:

ANDing the first and second registers to determine when the pointer points to a port for which an indication has been stored.

17. A method of arbitrating among equal priority signals from a plurality of ports in an InfiniBand switch, the method comprising:

storing an indication of a port issuing the signal along with an indication of the type of signal;

cycling a pointer though each port and each type of signal; and

when the pointer points to a port for which an indication has been stored, processing the signal from that port.